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參數(shù)資料
| 型號： | MU9C8K64-90TDI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MU9C Routing Coprocessor (RCP) Family |
| 中文描述： | MU9C路由協(xié)處理器（RCP）的家庭 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 611K |
| 代理商： | MU9C8K64-90TDI |
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MU
9
C Binary Routing Coprocessor (RCP) Family
Control State Descriptions
16
Rev.
6
CONTROL STATE DESCRIPTIONS
REGISTER READ/WRITE
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: n/a
Description:
No operation. The device performs no
operation during the cycle. No existing states change. DSC
must be LOW.
No Operation
NOP Binary
XXX XXX 000 011
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: n/c Scope: NFD
Description:
Reads the value of the Next Free address on
the DQ11–0/DQ12–0 bus. In a vertically cascaded system
this will be in the device whose /FI=LOW and /FF=HIGH,
and at the highest-priority location whose Validity bit is
set HIGH. This value is the address of the location where a
subsequent Write at Next Free Address cycle will be
written. The Page address of the device value is output
DQ19–16; DQ31–20 are LOW. DSC must be LOW.
Read Next Free Address
RD NFA
XXX XXX 000 011
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description:
Writes data from the DQ31–0 bus to the
Address register. The write is masked by the contents of
Mask Register nnn. When nnn=000 no mask is used; when
masking is selected, only bits in the addressed location
that correspond to LOW values in the selected mask
register are updated. DSC must be LOW.
Write Address Register
WR AR{MRnnn}
XXX nnn 000 100
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S
Description:
Reads the contents of the Address register to
the DQ31–0 bus. DSC must be LOW.
Read Address Register
RD AR
XXX XXX 000 100
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description:
Writes data from the DQ31–0 bus to the
Configuration register. The write is masked by the
contents of Mask Register nnn. When nnn=000 no mask is
used; when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated. DSC must be LOW.
Write Configuration Register
WR FR{MRnnn}
XXX nnn 000 110
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S
Description:
Reads the contents of the Configuration
register to the DQ31–0 bus. DSC must be LOW.
Read Configuration Register
RD FR
XXX XXX 000 110
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description:
Writes data from the DQ31–0 bus to the
Device Select register. The write is masked by the contents
of Mask Register nnn. When nnn=000 no mask is used;
when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated. DSC must be LOW.
Write Device Select Register
WR DS{MRnnn}
XXX nnn 001 000
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH AV: HIGH PA:AA: n/c Scope: S
Description:
Reads the contents of the Device Select
register to the DQ31–0 bus. DSC must be LOW.
Read Device Select Register
RD DS
XXX XXX 001 000
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: n/c Scope: HPD/S
Description:
Reads the contents of the Status register to
the DQ31–0 bus. After a Comparison or Read/Write at
Highest-Priority Matching Address cycle only the
highest-priority device with a match responds to this
control state; in the event of a mismatch, the
lowest-priority device responds. After a random access
Read or Write cycle into the Memory array, RD SR will
take place in any selected device. DSC must be LOW.
Read Status Register
RD SR
XXX XXX 000 111
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description:
Writes data from the DQ31–0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the
Comparand register. The write is masked by bits 31–0
(DSC LOW) or 63-32 (DSC HIGH) of Mask Register nnn.
When nnn=000 no mask is used; when masking is
selected, only bits in the addressed location that
correspond to LOW values in the selected mask register
are updated.
Write Comparand Register
WRs CR{MRnnn}
XXX nnn 000 101
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