參數(shù)資料
型號(hào)： MU9C4K64-90TDC
廠商： Electronic Theatre Controls, Inc.
英文描述： MU9C Routing Coprocessor (RCP) Family
中文描述： MU9C路由協(xié)處理器（RCP）的家庭
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 611K
代理商： MU9C4K64-90TDC
Register Descriptions
MU
9
C Binary Routing Coprocessor (RCP) Family
Rev.
6
13
the daisy chain with a delay through each stage. The
compare time in each device operating in parallel is added
to the ripple delay through the daisy chain. Before reading
the results of a comparison from the System Match flag,
the daisy chain must be given time to settle to a valid state.
If there are N devices vertically cascaded in a system, and
the time to get a valid output on /MF for one device is
t(MF), and the propagation delay for the flag to ripple
through one device from /MI valid to /MF valid is t(PD),
then the time t(DC) for the daisy chain to develop a valid
output condition is:
This period of time must elapse before the flagged results
of the comparison are available, and before /OE is driven
LOW or a Status Register Read cycle is performed.
There is a similar but shorter delay for the Full Flag daisy
chain, but this only limits the rate at which back-to-back
Write at Next Free Address cycles can be performed.
External Prioritization
For systems where the propagation delay associated with
the Match Flag daisy chain is unacceptable, the MU
9
C
RCP supports external prioritization. Using external
prioritization, each /MF output is fed to a 1 of N
prioritizing circuit whose outputs are fed back to the /CS
and /OE inputs of the respective MU
9
C RCPs. A ccess to
the Highest-Priority Match Memory location or Status
register is accomplished by only enabling the /CS to the
Highest-Priority Match device based on the status of the
/MF flags in the system. Likewise, access to the
Highest-Priority Match device’s PA:AA bus match
address result is accomplished by enabling only the /OE
line to the Highest-Priority Match device.
Initialization
After power is applied to the MU
9
C RCP the /RESET
line must be pulled LOW for at least 50 ns to ensure that
the device establishes its correct initial operating
conditions. There are control states to initialize the
system-level operating conditions that can be run once the
device or devices in the system have been reset after
power has been applied.
Reset
The Reset condition occurs when the /RESET line is
pulled LOW (Hardware reset,) or when the Reset Control
state is executed (Software reset.) The conditions after a
reset are shown in Table 2.
The Instruction register is enabled for Software Control
mode. To activate Hardware control, the appropriate value
should be written to the Configuration register in two
cycles from the DQ31–0 lines.
For a Hardware reset, FR25, which defines the lowest
priority device, is set HIGH. This means that either FR25
must be set LOW in the lowest-priority device, or a
Memory access cycle or a Compare cycle that generates a
match must be executed for there to be any response when
reading the PA:AA bus or the Status register.
System Initialization
Once the MU
9
C RCP devices in the system have been
reset, the system operating conditions must be set up. The
MU
9
C RCP is reset to Software Control mode, so a value
must be written to the Configuration register to set the
persistent operating state of the device. This first write to
the devices in the system must be through Software
control. The following sequence writes a new value to the
Configuration register under software control:
1. Write
DQ13=LOW).
The value 006H is the control state Write to
Configuration register, WR FR, with no mask. /AV
being HIGH indicates that this is the instruction to be
written to the Instruction register, and DQ13 being
LOW indicates that it is a Write cycle.
006H
to
MU
9
C
RCPs
(/AV=HIGH,
2. Write XXXXXXXXH to MU
9
C RCPs (/AV=LOW).
The value XXXXXXXXH is written to the
Configuration register, and if FR27–26=00 then the
devices are set to operate in Hardware Control mode.
/AV being LOW causes the control state to execute
using the data present on the DQ31–0 lines.
If the devices in a vertically cascaded system are to be
selected solely through the Device Select register, then the
Page addresses must be set to unique values in each
device. However, to set the Page address in each
Configuration register in turn would require that each
device already had a unique Page Address value. To
overcome this dilemma, there are two special control
states that allow the Page Address registers to be set
individually in this circumstance. Once the general
operating
conditions
have
broadcasting a configuration value to all the MU
9
C RCPs
in the system, the Page Address values must be set to a
unique value in each device. This is done through a
sequence of WR PA control states, each executed with a
unique value on the DQ31-0 lines. This control state
writes the DS3–0 value into the Page Address field of the
Configuration register of the highest-priority empty
device, and then sets the Full flag of that device to indicate
full (LOW). The next WR PA will therefore be directed to
the next lower-priority device within the system. The
sequence continues until all Page Address values have
been written. The RST FF control state is then broadcast to
all devices to set the Full flags back to Empty, and the
system is then ready for normal operation.
been
established
by
t(DC) = t(MF)+(N-1)*t(PD)
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