參數(shù)資料
型號: MU9C4K64-12TDC
廠商: Electronic Theatre Controls, Inc.
英文描述: MU9C Routing Coprocessor (RCP) Family
中文描述: MU9C路由協(xié)處理器(RCP)的家庭
文件頁數(shù): 26/30頁
文件大?。?/td> 611K
代理商: MU9C4K64-12TDC
MU
9
C Binary Routing Coprocessor (RCP) Family
Electrical
26
Rev.
6
Switching Characteristics
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
-1.0V for a duration of 10ns measured from the 50% amplitude points (see Figure 6) for input-only lines.
Common I/O lines are clamped so that transients cannot fall below -0.5V.
Applies to all cycle types except Compare cycles and Memory Read cycles (memory to DQ).
Applies to Compare cycles (including NEXT).
Control signals are /CS1, /CS2, /W, /AV, DSC, and the AC bus.
With loads specified in Figure 5, Test load A from Table 7.
With loads specified in Figure 5, Test load B from Table 7.
/E should be HIGH during /RESET active to ensure proper device defaults.
Test inputs are the TDI and TMS signals.
With output and I/O pins unloaded
Pins with internal pull-ups are /RESET, TCLK, TMS, TDI, and /TRST.
-35
-40
-50
-70
-90
-12
No Symbol
1a tELEL
1b tELEL
2a tELEH
2b tELEH
3
tEHEL
4
tCVEL
5
tELCX
6
tELQX
7
tELQV
Parameter (all times in nanoseconds)
Chip Enable Cycle Time (Other Cycles)
Chip Enable Cycle Time (Compare Cycle)
Chip Enable LOW Pulse Width (Other Cycles)
Chip Enable LOW Pulse Width (Compare Cycle)
Chip Enable HIGH Pulse Width
Control Input to Chip Enable LOW Setup Time
Control Input to Chip Enable LOW Hold Time
Chip Enable LOW to Outputs Active
Chip Enable LOW to Outputs Valid
Min Max Min Max Min Max Min Max Min Max Min Max Notes
40
40
50
50
35
40
50
70
30
30
40
40
25
30
40
60
9
10
10
10
5
5
5
5
4
4
4
4
5
5
5
5
30
35
40
35
40
50
2
10
2
10
2
10
2
4
4
4
4
4
4
4
4
n/a
5
5
5
0
0
0
0
5
6
8
15
15
16
2
2
2
2
15
18
22
4
6
8
8
2
2
2
2
12
14
15
15
15
15
42
50
60
5
6
8
7
7
8
2
10
2
10
2
10
2
8
10
12
3
3
3
3
3
3
3
3
10
15
20
20
25
30
50
50
10
15
20
20
20
20
20
20
20
20
20
20
2
10
2
10
2
10
2
50
90
40
75
10
8
4
5
75
120
55
90
10
10
5
5
3
4
3
4
5
5
6
6
6
7
6
Register
Memory
40
50
10
40
70
10
50
80
15
8
9
tEHQZ
tDVEL
Chip Enable HIGH to Outputs High-Z
Data to Chip Enable LOW Setup Time
Data from Chip Enable LOW Hold Time
2
4
4
5
0
2
5
5
5
3
10 tELDX
Commercial
Industrial
11 tFIVEL
12 tFIVFFV
13 tEHFFV
14 tEHQX
15 tEHQV
16 tMIVEL
17 tEHMX
18 tEHMV
Full In Valid to Chip Enable LOW Setup Time
Full In Valid to Full Flag Valid
Chip Enable HIGH to Full Flag Valid
Chip Enable HIGH to Output Change
Chip Enable HIGH to Output Valid
Match In Valid to Chip Enable LOW Setup
Chip Enable HIGH to Match Flag Change
Chip Enable HIGH to Match Flag Valid
8
9
12
25
16
16
2
2
22
25
30
10
2
12
2
/MF
/MM
17
17
n/a
8
8
10
12
20
20
n/a
9
9
10
14
25
25
n/a
12
12
15
16
19 tELMV
20 tMIVMV
Chip Enable LOW to Match Flag Valid
Match In Valid to Match Flag Valid
/MF
/MM
21 tOEHQZ
22 tOELQV
23 tMIVOEL
24 tFIVOEL
25 tEHRSTL
26 tRSTLRSTH
27 tRSTHEL
28 tTIVTCLKH
29 tTCLKHTIX
30 tTCLKLT-
DOX
31 tTCLKLT-
DOV
32 tTCLKLT-
DOZ
Output Enable HIGH to Outputs High-Z
Output Enable LOW to Match Address Outputs Valid
Match in Valid to Output Enable LOW
Full in Valid to Output Enable LOW
Chip Enable HIGH to Reset LOW
Reset Pulse Width
Reset HIGH to Chip Enable LOW
Test Input Valid to TCLK HIGH Setup Time
TCLK HIGH to Test Input Hold Time
TCLK LOW to TDO Change
2
2
3
3
20
50
20
20
20
2
4
4
25
70
25
25
25
2
8
9
9
10
10
15
TCLK LOW to TDO Valid
20
20
20
20
20
25
TCLK LOW to TDO High-Z
20
20
20
20
20
25
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