參數(shù)資料
型號(hào)： MU9C1902-25EC
英文描述： x9 Asynchronous FIFO
中文描述： X9熱賣異步FIFO
文件頁(yè)數(shù)： 21/28頁(yè)
文件大?。?/td> 246K
代理商： MU9C1902-25EC
MU9C1480A/L Draft
Rev. 3.0 Draft
21
Table 8: Control Register Bit Assignments
Note:
D15 reads back as 0.
15
14 13
12 11
10 9
8 7 6
5 4
3 2
1 0
RST
R
E
S
E
T
=
0
Match Flag
Enable
=00
Disable
= 01
No Change
= 11
Full Flag
Enable
= 00
Disable
= 01
No Change
= 11
Translation
Input Not
Translated
= 00
Input
Translated
= 01
No Change
= 11
CAM/RAM Part.
64 CAM/0 RAM = 000
48 CAM/16 RAM = 001
32 CAM/32 RAM = 010
16 CAM/48 RAM = 011
48 RAM/16 CAM = 100
32 RAM/32 CAM = 101
16 RAM/48 CAM = 110
No Change = 111
Comp. Mask
None = 00
MR1 = 01
MR2 = 10
No Change
= 11
AR Inc/Dec
Increment
= 00
Decrement
= 01
Disable
= 10
No Change
= 11
Mode
Standard
= 00
Enhanced
= 01
Reserved
= 10
No Change
= 11
INSTRUCTION SET SUMMARY Continued
REGISTER BIT ASSIGNMENTS
Table 7: Instruction Cycle Lengths
CYCLE
LENGTH
Short
Medium
Long
Command Read
Status register or
16-bit register
Data Write
Comparand register
(not last segment)
Mask register
(not last segment)
Memory array
(NFA invalid)
Memory array
(NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
Data Read
Comparand register
Mask register
Memory array
Note:
The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics section under the
tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as the source or destination), the
first cycle is short, and the second cycle will be the length given.
CYCLE TYPE
Command write
MOV reg, reg (except L-70)
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
SBR, RSC
NOP (except L-70)
SFT (A)
MOV reg, mem
MOV reg, reg (L-70)
TCO CT (reset)
VBC (NFA invalid)
SFT (L)
NOP (L-70)
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
SFF
VBC (NFA valid)
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