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| 型號： | MU9C1485-12TCC |
| 英文描述： | Content Addressable Memory |
| 中文描述： | 內(nèi)容可尋址存儲器 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 246K |
| 代理商： | MU9C1485-12TCC |
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MU9C1480A/L Draft
Rev. 3.0 Draft
15
OPERATIONAL CHARACTERISTICS Continued
Table 5a (Standard mode) and Table 5b (Enhanced mode)
show when a device will respond to reads or writes and
when it will not, based on the state of /EC(int), the internal
match condition, and other control inputs. /EC is latched
by the falling edge of /E. /EC(int) is registered from the
latched /EC signal off the rising edge of /E, so it controls
what happens in the next cycle, as shown in Figure 6. When
/EC is first taken LOW in a string of LANCAM devices
(and assuming the Device Select registers are set to FFFFH),
all devices will respond to that command write or data write.
From then on the daisy chain will remain locked in each
subsequent cycle as long as /EC is held LOW on the falling
edge of /E in the current cycle. When the daisy chain is
locked in Standard mode, only the Highest-Priority Match
device will respond (See Case 6 of Table 5a). If, for example,
all of the CAM memory locations were empty, there would
be no match, and /MF would stay HIGH. Since none of the
devices could then be the Highest-Priority Match device,
none will respond to reads or writes until the daisy chain is
unlocked by taking /EC HIGH and asserting /E for a cycle.
If there is a match between the data in the Comparand
register and one or more locations in memory, then only the
Highest-Priority Match device will respond to any cycle,
such as an associated data or Status Register read. If there
is not a match, then a NOP with /EC HIGH needs to be
inserted before issuing any new instructions, such as Write
to Next Free Address instruction to learn the data. Since
Next Free operations are controlled by the /FI–/FF daisy
chain, only the device with the first empty location will
respond. If an instruction is used to unlock the daisy chain
it will work only on the Highest-Priority Match device, if
one exists. If none exists, the instruction will have no effect
except to unlock the daisy chain. To read the Status registers
of specific devices when there is no match requires the use
of the TCO DS command to set DS=PA of each device.
Single chip systems can tie /EC HIGH and read the Status
register or the /MA and /MM pins to monitor match
conditions, as the daisy chain lock-out feature is not needed
in this configuration. This removes the need to insert a
NOP in the case of a no-match.
When the Control register is set to Enhanced mode, you
can continue to write data to the Comparand register or
issue a Move to Next Free Address instruction without
first having to issue a NOP with /EC HIGH to unlock the
daisy chain after a Compare cycle with no match, as indicated
in cases 4 and 5 of Table 5b on page 12. In Enhanced mode,
data write cycles as well as command write cycles are
enabled in all devices even when /EC is LOW. Exceptions
are data writes, moves, or VBC instructions involving HM,
which occur only in the device with the highest match; and
data writes or move instructions involving NF, which occur
only in the device with /FI LOW and /FF HIGH. Enhanced
mode speeds up system performance by eliminating the
need to unlock the daisy chain before Command or Data
Write cycles.
Full Flag Cascading
The Full Flag daisy chain cascading is used for three
purposes: first, to allow instructions that address Next Free
locations to operate globally; second, to provide a system
wide Full flag; third, to allow the loading of the Page
Address registers during initialization using the SFF
instruction. The full flag logic causes only the device
containing the first empty location to respond to Next Free
instructions such as “MOV NF,CR,V”, which will move the
contents of the Comparand register to the first empty
location in a string of devices and set that location Valid,
so it will be available for the next automatic compare. With
devices connected as in Figure 1a on page 7, the /FF output
of the last device in a string provides a full indication for
the entire string.
IEEE 802.3/802.5 Format Mapping
To support the symmetrical mapping between the address
formats of IEEE 802.3 and IEEE 802.5, the LANCAM provides
a bit translation facility. Formally expressed, the nth input
bit, D(n), maps to the xth output bit, Q(x), through the
following expressions:
D(n) = Q(7–n) for 0 < n < 7,
D(n) = Q(23–n) for 8 < n < 15
Setting Control Register bit 10 and bit 9 selects whether to
persistently translate, or persistently not to translate, the
data written onto the 64-bit internal bus. The default
condition after a Reset command is not to translate the
incoming data. Figure 2 on page 8 shows the bit mapping
between the two formats.
INITIALIZING THE LANCAM
Initialization of the LANCAM is required to configure the
various registers on the device. Since a Control register
reset establishes the operating conditions shown in Table
4 on page 10, restoration of operating conditions better
suited for the application may be required after a reset,
whether using the Control Register reset, or the /RESET
pin. When the device powers up, the memory and registers
are in an unknown state, so the /RESET pin must be asserted
to place the device in a known state.
Setting Page Address Register Values
In a vertically cascaded system, the user must set the
individual Page Address registers to unique values by
using the Page Address initialization mechanism. Each Page
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