參數(shù)資料
型號(hào)： MU9C1480B-90TAI
英文描述： Content Addressable Memory
中文描述： 內(nèi)容可尋址存儲(chǔ)器
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 246K
代理商： MU9C1480B-90TAI
MU9C1480A/L Draft
Rev. 3.0 Draft
7
instructions are active only for one Command Read or
Write cycle after being loaded into the Instruction decoder.
The data and control interfaces to the LANCAM are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the
Destination Segment counter is clocked by the rising edge
of /E. During a Read cycle, the Control inputs are registered
by the falling edge of /E, and the Data outputs are enabled
while /E is LOW. When reading from the persistently
selected data source, the Source Segment counter is
clocked by the rising edge of /E.
THE REGISTER SET
The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set and
the other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
active after a reset. Having two alternate sets of registers
that determine the device configuration allows for a rapid
return to a foreground network filtering task from a
background housekeeping task.
Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.
Instruction Decoder
The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles. If an instruction’s Address Field flag (bit 11)
is set to a 1, it is a two-cycle instruction that is not executed
immediately. For the next cycle only, the data from a
Command Write cycle is loaded into the Address register
and the instruction then completes at that address. The
Address register will then increment, decrement, or stay at
the same value depending on the setting of Control Register
bits CT3 and CT2. If the Address Field flag is not set, the
memory access occurs at the address currently contained
in the Address register.
Figure 1a: Vertical Cascading
Figure 1b: External Prioritizing
Vcc
SYSTEM FU LL
SYSTE M MATC H
/MI
/FI
/FF
/MF
LAN C AM
16
/E
/W
/C M
/EC
D Q15–0
/MI
/FI
/FF
/MF
/MI
/FI
/FF
/MF
/E
/W
/C M
/EC
D Q15–0
/E
/W
/C M
/EC
D Q15–0
/E
/W
/C M
/EC
D Q15–0
LAN C AM
LAN C AM
OPERATIONAL CHARACTERISTICS Continued
/MA
/MA
/MA
/MA
LANCAM
/MI
/MI
/MI
/MI
Vcc
SYSTEM
MATCH
PLD
LANCAM
LANCAM
LANCAM
相關(guān)PDF資料
PDF描述
MU9C1480L-12DC Content Addressable Memory
MU9C1480L-12DI Content Addressable Memory
MU9C1480L-70DC Content Addressable Memory
MU9C1480L-70DI Content Addressable Memory
MU9C1480L-90DC Content Addressable Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MU9C1480L 制造商:MUSIC 制造商全稱:MUSIC Semiconductors 功能描述:TQFP Package Option
MU9C1480L-12DC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory
MU9C1480L-12DI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The 1024 x 64-bit LANCAM facilitates numerous 1024 x 64-bit CMOS content-addressable memory (CAM)
MU9C1480L-70DC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory
MU9C1480L-70DI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory
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