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參數(shù)資料
| 型號： | MTV412MS128 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Monitor Controller 128K Flash Type with ISP |
| 中文描述： | 8051嵌入式控制器的ISP監(jiān)控128K閃存式 |
| 文件頁數(shù)： | 18/26頁 |
| 文件大?。?/td> | 255K |
| 代理商： | MTV412MS128 |
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MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
INTFLG
(w) :
Revision 0.9 - 18 - April 2002
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serving the interrupt routine.
SlvBMI = 1
→
No action.
= 0
→
Clears SlvBMI flag.
STOPI = 1
→
No action.
= 0
→
Clears STOPI flag.
ReStaI = 1
→
No action.
= 0
→
Clears ReStaI flag.
WslvA1I = 1
→
No action.
= 0
→
Clears WslvA1I flag.
WslvA2I = 1
→
No action.
= 0
→
Clears WslvA2I flag.
MbufI = 1
→
No action.
= 0
→
Clears Master IIC bus interrupt flag (MbufI).
INTFLG
(r) :
Interrupt flag.
= 1
TXBI
RCBI = 1
→
Indicates the TXBBUF need a new data byte, cleared by writing TXBBUF.
→
Indicates the RCBBUF has received a new data byte, cleared by reading
RCBBUF.
→
Indicates the slave IIC address B match condition.
→
Indicates the slave IIC has detected a STOP condition for HSCL1/HSDA1 pins.
→
Indicates the slave IIC has detected a repeat START condition for HSCL1/HSDA1
pins.
→
Indicates the slave A1 IIC has detected a STOP condition of write mode.
→
Indicates the slave A2 IIC has detected a STOP condition of write mode.
→
Indicates a byte is sent/received to/from the master IIC bus.
SlvBMI = 1
STOPI = 1
ReStaI = 1
INTEN
(w) :
WslvA1I = 1
WslvA2I = 1
MbufI = 1
Interrupt enable.
ETXBI = 1
ERCBI = 1
ESlvBMI = 1
ESTOPI = 1
EReStaI = 1
EWSlvA1I = 1
→
Enables slave A1 IIC bus STOP of write mode interrupt.
EWSlvA2I = 1
→
Enables slave A2 IIC bus STOP of write mode interrupt.
EMbufI = 1
→
Enables Master IIC bus interrupt.
→
Enables TXBBUF interrupt.
→
Enables RCBBUF interrupt.
→
Enables slave address B match interrupt.
→
Enables IIC bus STOP interrupt.
→
Enables IIC bus repeat START interrupt.
Mbuf
(w) :
Master IIC data shift register, after START and before STOP condition, write this register
resumes MTV412M's transmission to the IIC bus.
Mbuf
(r) :
Master IIC data shift register, after START and before STOP condition, read this register
resumes MTV412M's reception from the IIC bus.
DDCCTRA1
(w) : DDC interface control register for HSCL1, HSDA1 pins.
DDC1en = 1
→
Enables DDC1 data transfer in DDC1 mode.
= 0
→
Disables DDC1 data transfer in DDC1 mode.
En128W = 1
→
The lower 128 bytes (00-7F) of DDCRAM1 can be written by IIC master.
= 0
→
The lower 128 bytes (00-7F) of DDCRAM1 cannot be written by IIC master.
En256W = 1
→
The higher 128 bytes (80-FF) of DDCRAM1 can be written by IIC master.
= 0
→
The higher 128 bytes (80-FF) of DDCRAM1 cannot be written by IIC master.
Only128 = 1
→
The SlaveA1 always accesses EDID data from the lower 128 bytes of DDCRAM1.
= 0
→
The SlaveA1 accesses EDID data from the whole 256 bytes DDCRAM1.
SlvA1bs1,SlvA1bs0 : Slave IIC block A1's slave address length.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTV412MV128 | 8051 Embedded Monitor Controller 128K Flash Type with ISP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTV412MV128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded Monitor Controller 128K Flash Type with ISP |
| MTV-50 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Two-Way Power Dividers, 1 - 100 MHz and 40 - 400 MHz |
| MTV50CD35 | 制造商:Mallory Sonalert Products Inc 功能描述:Molded Case Vertical-Mount Electrolytic Radial Leads Capacitor - 50uF 35dcV -10+100% |
| MTV-50PIN | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Two-Way Power Dividers 1 - 100 MHz and 40 - 400 MHz |
| MTV-50-PIN | 功能描述:信號調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
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