- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376207 > MTV004 (Electronic Theatre Controls, Inc.) On-Screen Display Shrink Version PDF資料下載
參數(shù)資料
| 型號： | MTV004 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | On-Screen Display Shrink Version |
| 中文描述： | 屏幕顯示收縮版本 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 88K |
| 代理商： | MTV004 |
MYSON
TECHNOLOGY
MTV004
MTV004 Revision 4.0 06/24/1999
4/9
transmission efficiency. Row and column addresses are incremented automatically when format (c) is applied.
Furthermore, the locations in columns 24-29 should be filled with dummy data.
The MSB (b7) bit is used to distinguish row and column addresses when transferring data from the external
controller. The b6 bit is used to differentiate column addresses for formats (a), (b) and (c), respectively. The
address configuration is shown in Table 1.
Table 1. Address Configuration in Interface
Address
Row
Columnab
Columnc
b7
1
0
0
b6
x
0
1
b5
x
x
x
b4
x
C4
C4
b3
R3
C3
C3
b2
R2
C2
C2
b1
R1
C1
C1
b0
R0
C0
C0
Format
a,b,c
a,b
c
The data transmission is permitted to change from format (a) to formats (b) and (c), or from format (b) to format
(a), but not from format (c) back to formats (a) and (b). The alternation between formats is configured according
to the state diagram shown in Figure 4.
Initiate
ROW
COL
c
COL
ab
DA
c
DA
ab
1, X
0 1
0 0
X X
X X
0 1
1, X
1, X
format (a)
format (b)
format (c)
X, X
0, X
Input = b7, b6
0, 0
Figure 4. Format State Diagram
3.2 Address Bus Administrator
The administrator manages bus address arbitration of display registers (RAM) during external data writing or
internal display control. The external data writing through the serial data interface to RAM must be
synchronized by internal display timing. In addition, the administrator also provides automatic incrementing to
the address bus when external writing using format (c) and the full-screen display control are applied.
3.3 Vertical Control Logic
The vertical logic generates different vertical display sizes for most display standards in current monitors. The
vertical display size is calculated using the information of the double character height bit (CHS) and vertical
display height control registers (CH5-CH0). The algorithm of the repeating character line display is shown in
Tables 2 and 3. The programmable vertical size range is 160 lines to maximum 1260 lines.
相關PDF資料 |
PDF描述 |
|---|---|
| MTV012A | 8051 Embedded CRT Monitor Controller Mask Version |
| MTV012E | 8051 Embedded CRT Monitor Controller OTP Version |
| MTV018 | IC TXRX PHY 10/100 3.3V 48LQFP |
| MTV021 | Enhanced Super On-Screen Display |
| MTV021N20 | Enhanced Super On-Screen Display |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MTV012A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded CRT Monitor Controller Mask Version |
| MTV012E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded CRT Monitor Controller OTP Version |
| MTV016 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced On-Screen-Display Controller |
| MTV016N-10 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
| MTV016N-18 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
發(fā)布緊急采購，3分鐘左右您將得到回復。