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參數(shù)資料
| 型號(hào)： | MTU429B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 4-Bit Micro-Controller with LCD Dr |
| 中文描述： | 4位微控制器與LCD博士 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 173K |
| 代理商： | MTU429B |
4/20
MTU429B Revision 3.0 28/Oct/1999
MTU429B
(Preliminary)
MYSON
TECHNOLOGY
3.0 PAD DESCRIPTIONS
Name
I/O
Description
BAK
Positive backup voltage.
In Li mode, connects a 0.1u capacitance to GND.
LCD drive voltage and positive supply voltage.
While in Ag mode, connects +1.5V to VDD1.
While in Li/ExtV mode, connects +3.0V to VDD2.
Input pin for LSI reset signal.
With Internal pull-down resistor.
Input pin for external INT request signal.
Falling edge or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or floatting to be selected by mask option.
Test signal input pin, internal pull-down resistor.
Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3, 4 pins. Con-
nects the CUP1, CUP2 and CUP3 pins with a nonpolarized electronic capacitor if 1/
2, 1/3 or 1/4 bias mode has been selected. In the STATIC mode, these pins should
be open.
Time based counter frequency (Clock specified. LCD alternating frequency. Alarm
signal frequency.) or system clock oscillation.
32KHz crystal oscillator.
Oscillation stops at the execution of STOP instruction.
System clock oscillation.
Connected with ceramic resonator.
Connected with RC oscillation circuit.
Oscillation stops at the execution of STOP or SLOW instruction.
Output pins for supplying voltage to drive the common pins of the LCD panel.
Output pins for LCD panel segment.
Output pins for LCD panel segment.
Key strobe function, share pins as key scan output.
Output pins for LCD panel segment.
Input/Output port A, can use software to define the internal pull-low resistor and
chattering clock in order to reduce input bounce and generate an interrupt.
This port shares pins with SEG35~38 and is set by mask option.
This port also shares pins with CC, RR, RT and RH, and is set by mask option.
Input/Output port B.
IOB port shares pins with SEG31~34, and is set by mask option.
This port also shares pins with ELC, ELP, BZB and BZ, and is set by mask option.
Input/Output port C, can use software to define internal pull-low / low-level hold
resistor and chattering clock in order to reduce input bounce and generate an inter-
rupt or key_board scanning function with ELC, ELP, BZB and BZ, and is set by
mask option.
Input/Output port D.
This port shares pins with SEG27~30 and is set by mask option.
IOD3, 4 shares pins with PWM1, 2 and is set by mask option.
Input ports by mask option to internal pull-low/low-level hold resistor and chattering
clock in order to reduce input bounce and generate an interrupt or Halt or stop
Release.
VDD1, 2, 3, 4
RESET
I
INT
I
TESTA
I
CUP1, 2, 3
O
XTIN
XTOUT
I
O
CFIN
CFOUT
I
O
COM1~8
SEG1~10
SEG11~26 /
KO1~16
SEG27~42
O
O
O
O
IOA1~4
I/O
IOB1~4
I/O
IOC1~4
I/O
IOD1~4
I/O
S1~4
I
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