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參數(shù)資料
| 型號： | MT93L00A |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Multi-Channel Voice Echo Canceller |
| 中文描述： | 多通道語音回聲消除器 |
| 文件頁數(shù)： | 5/39頁 |
| 文件大小： | 636K |
| 代理商： | MT93L00A |
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MT93L00A
Data Sheet
5
Zarlink Semiconductor Inc.
R7
13
DTA
Data Transfer Acknowledgment (Open Drain Output)
. This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1 K typical) is required at this output.
T2,T4,T6,T8,T9,T11,
T13,T15
15,16,17,
19,20,21,
22,23
D0 - D3,
D4 - D7
Data Bus D0 - D7 (Bidirectional)
. These pins form the 8-bit
bidirectional data bus of the microprocessor port.
P16,N16,M16,L16,K16,
J16,H16,G16,F16,E16,
D16
28,29,30,31,
33,34,35,36,
38,39,40
A0 - A10
Address A0 to A10 (Input)
. These inputs provide the A10 - A0
address lines to the internal registers.
B13
57
ODE
Output Drive Enable (Input).
This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
A8
58
Sout
Send PCM Signal Output (Output)
. Port 1 TDM data output
streams.
Sout pin outputs serial TDM data streams at 2.048 Mbps with 32
channels per stream.
B9
59
Rout
Receive PCM Signal Output (Output)
. Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at
2.048 Mbps with 32 channels per stream.
B11
60
Sin
Send PCM Signal Input (Input).
Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mbps with 32
channels per stream.
B7
61
Rin
Receive PCM Signal Input (Input).
Port 1 TDM data input
streams.
Rin pin receives serial TDM data streams at 2.048 Mbps with 32
channels per stream.
B5
62
F0i
Frame Pulse (Input).
This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
A4
63
C4i
Serial Clock (Input).
4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
G2
90
MCLK
Master Clock (Input).
Nominal 10 MHz or 20 MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
H2
92
Fsel
Frequency select (Input).
This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 19.2 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 9.6 MHz Master Clock input must be applied.
Pin Description (continued)
PIN #
PIN
Name
Description
208-Ball LBGA
100 PIN
LQFP
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| MT93L00AB | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.164/G.165/G.168/G.711 W/ TONE DET - Trays |
| MT93L00AV | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.164/G.165/G.168/G.711 W/ TONE DET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCELLER 208PBGA 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCELLER 208PBGA |
| MT93L04 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller |
| MT93L04A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller |
| MT93L04AG | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 128CH G.164/G.165/G.168/G.711 W/ TONE DE - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 365MCMBGA |
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