參數(shù)資料
型號: MT933
廠商: Zarlink Semiconductor Inc.
英文描述: 3.3V 10/100 Fast Ethernet Transceiver to MII
中文描述: 3.3 10/100快速以太網(wǎng)收發(fā)器,以信息產(chǎn)業(yè)部
文件頁數(shù): 3/20頁
文件大小: 360K
代理商: MT933
2
MT933
Figure 2Pin connections
TP64
48 MINT
47 DVDD3
46 MDC
45 MDIO
44 DGND3
43 RefCLK
42 OSCVDD
41 XTAL1
40 XTAL2
39 OSCGND
38 TXGND4
37 TXVDD4
36 TXREF100
35 TXREF10
34 TXVDD3
33 TXGND3
S
P
P
P
T
T
T
T
T
T
A
R
R
R
P
RXGND2 16
RESETN 14
PA4 13
SPDST 12
RXFDST 11
RXVDD3 9
DVDD1 8
COLST 7
ACTST 6
TX_EN 4
DGND1 3
TX_ER 2
SUBGND2 1
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
Functional Description
The MT933 has three basic modes of operation:
10BASE-T, 100BASE-TX and LOW POWER modes.
The Control block is designed to manage these
modes by starting and stopping the 10M and 100M
transceivers in a well-controlled manner such that no
spurious signals are output on either the MII or
twisted-pair interfaces. Furthermore, it continuously
monitors the behaviour of the transceivers and takes
corrective action if a fault is detected.
Other modes described herein are repeater mode
and reset mode.
25MHz Reference Clock
The MT933 requires a 25MHz +/-100ppm timing
reference for 802.3 compatible operation. This may
be supplied either from the integrated oscillator or
from an external source. When the integrated oscillator
is used, a suitable crystal must be connected across
the XTAL1 & XTAL2 pins (see “External Components”)
and REFCLK must be tied low. When an external
source is used, it must be input to the REFCLK pin
and XTAL1 must be tied low. XTAL2 must be
unconnected.
10Base-T Operation
10Mb/s Data Transfer on the MII
10Mb/s data is transferred across the MII with clock
speeds of 2.5MHz. The MAC outputs data to the
MT933 via the MII interface, on the TXD[3:0] bus.
This data is synchronised to the rising edge of
TX_CLK. To indicate that there is valid data for
transmission on the MII, the MAC sets the TX_EN
signal active. This forces the MT933 device to take in
the data on the TXD[3:0] bus. This is serialised and
directly encoded as Manchester data, before being
output on the TXOP/TXON differential output for
transmission through 1:2 magnetics and onto the
twisted-pair.
The transmit current is governed by the current through
the TXREF10 pin, which must be grounded through
a resistor as described in “External Components”.
RX10 Clock Recovery
The MT933 employs a digital delay line controlled by
the 100MHz Synthesizer DLL to derive a sampling
clock from the incoming signal. The recovered clock
runs at twice the data rate (nominally 20MHz). When
a signal is received from the Signal Detect block, it is
used to strobe Link Pulses and Manchester encoded
serial data.
相關(guān)PDF資料
PDF描述
MT933CG 3.3V 10/100 Fast Ethernet Transceiver to MII
MT933TP1N 3.3V 10/100 Fast Ethernet Transceiver to MII
MT93L00A Multi-Channel Voice Echo Canceller
MT93L04 128-Channel Voice Echo Canceller
MT9LD272G-6S x72 Fast Page Mode DRAM Module
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT933CG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII
MT933TP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII
MT938T17K26S001 制造商:Matrix 功能描述:Connector
MT938T17K26S-001 制造商:Matrix 功能描述:Connector
MT93L00A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller