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參數(shù)資料
| 型號(hào)： | MT9300BV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Multi-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封裝： | 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208 |
| 文件頁數(shù)： | 14/39頁 |
| 文件大?。?/td> | 629K |
| 代理商： | MT9300BV |
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MT9300B
Data Sheet
14
Zarlink Semiconductor Inc.
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back -to -Back configurations, MuteR and MuteS bits of Echo Canceller B must always
be “0”. Refer to Figure 4 and to Control Register 2 for bit description.
Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout.
When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero.
Bypass state must be selected for at least one frame
(125
μ
s) in order to properly clear the filter.
Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register A1/B1 and Control Register 2 through four control
bits: MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
MT9300B Throughput Delay
The throughput delay of the MT9300B varies according to the device configuration. For all device configurations,
Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout
and Sin to Sout paths have a delay of two frames.
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for
Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output
streams is for Rout pcm channels, and the other set is for Sout channels. See Figure 7 for channel allocation.
The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set
of PCM Send and Receive channels, as illustrated in Figure 4.
Figure 7 - ST-BUS and GCI Interface Channel Assignment for 2 Mb/s Data Streams
F0i
ST-Bus
Rin/Sin
Rout/Sout
Channel 31
Channel 0
125
μ
sec
Channel 1
Channel 30
F0i
GCI interface
Note: Refer to Figures 9 and 10 for timing details
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| MT9315AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
| MT933 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
| MT933CG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3.3V 10/100 Fast Ethernet Transceiver to MII |
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