參數(shù)資料
型號(hào)： MT9300B
廠商： Zarlink Semiconductor Inc.
英文描述： Multi-Channel Voice Echo Canceller
中文描述： 多通道語(yǔ)音回聲消除器
文件頁(yè)數(shù)： 13/39頁(yè)
文件大小： 629K
代理商： MT9300B
MT9300B
Data Sheet
13
Zarlink Semiconductor Inc.
Device Configuration
The MT9300B architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo
cancellers which can be individually controlled (Echo Canceller A and B). They can be set in three distinct
configurations:
Normal, Back-to-Back,
and
Extended Delay
. See Figure 6.
Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously.
Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 6c. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains undefined data. Back-to-Back configuration allows a no-glue interface for applications where bidirectional
echo cancellation is required.
Back-to-Back configuration is selected by writing “1” into the BBM bit of
both
Control Register A1 and Control
Register B1 of a given group of echo cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured
into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a
transmission device or between two codecs for echo control on analog trunks.
Extended Delay Configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 6b. This configuration uses only one timeslot on PORT1 and PORT2 and
the second timeslot normally associated with ECB contains undefined data.
Extended Delay configuration is selected by writing “1” into the ExtDl bit in Echo Canceller A, Control Register A1.
For a given group, only Echo Canceller A, Control Register A1, has the ExtDl bit. Control Register B1, bit-0 must
always be set to zero.
Table 2 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.
Echo Canceller Functional States
Each echo canceller has four functional states:
Mute, Bypass, Disable Adaptation
and
Enable Adaptation
.
Mute
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with
quiet code.
LINEAR
16 bits
2’s
complement
SIGN/
-
Law
A-Law
MAGNITUDE
CCITT (G.711)
μ
-
Law
A-Law
+Zero
(quiet code)
0000h
80h
FFh
D5h
Table 1 - Quiet PCM Code Assignment
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9300BL 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller
MT9300BV 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller
MT9315 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller
MT9315AE 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller
MT9315AP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller
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