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參數(shù)資料
| 型號(hào)： | MT9300 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| 中文描述： | 多通道語音回聲消除器（多通道話音回聲消除器） |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 110K |
| 代理商： | MT9300 |
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Advance Information
MT9300
9
Serial Data Interface Timing
The MT9300 provides ST-BUS and GCI interface
timing. The Serial Interface clock frequency, C4i, is
4.096 MHz. The input and output data rate of the ST-
Bus and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS
or GCI format. The MT9300 automatically detects
the presence of an input frame pulse and identifies it
as either ST-BUS or GCI. In ST-BUS format, every
second falling edge of the C4i clock marks a bit
boundary, and the data is clocked in on the rising
edge of C4i, three quarters of the way into the bit cell
(See Figure 9). In GCI format, every second falling
edge of the C4i clock marks the bit boundary, and
data is clocked in on the second falling edge of C4i,
half the way into the bit cell (see Figure 10).
Memory Mapped Control and Status
registers
Internal memory and registers are memory mapped
into the address space of the HOST interface. The
internal dual ported memory is mapped into
segments on a “per channel” basis to monitor and
control
each
individual
associated PCM channels. For example, in
Normal
configuration
, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the
internal address space from 0A0h to 0BFh and
interfaces to PCM channel #5 on all serial PCM I/O
streams.
echo
canceller
and
Figure 7 - Memory Mapping of per channel
Control and Status Registers
As illustrated in Figure 7, the “per channel” registers
provide independent control and status bits for each
echo canceller. Figure 8 shows the memory map of
the control/status register blocks for all echo
cancellers.
00hControl Reg A1
01h
Decay Step Size Reg
02h
03h
Base
Addr +
Echo Canceller A
04h
06h
Reserved
Flat Delay Reg
Control Reg 2
Status Reg
Reserved
05h
Reserved
08h
Decay Step Number
07h
Reserved
0Ah
Rin Peak Detect Reg
0Ch
Sin Peak Detect Reg
0Eh
Error Peak Detect Reg
10h
Reserved
12h
DTDT Reg
14h
Reserved
16h
NLPTHR
18h
Step Size, MU
1Ah
Reserved
1Ch
Reserved
1Eh
20hControl Reg B1
21h
Decay Step Size Reg
22h
23h
24h
26h
Reserved
Flat Delay Reg
Control Reg 2
Status Reg
Reserved
25h
Reserved
28h
Decay Step Number
27h
Reserved
2Ah
Rin Peak Detect Reg
2Ch
Sin Peak Detect Reg
2Eh
Error Peak Detect Reg
30h
Reserved
32h
DTDT Reg
34h
Reserved
36h
NLPTHR
38h
Step Size, MU
3Ah
Reserved
3Ch
Reserved
3Eh
Base
Addr +
Echo Canceller B
Figure 6 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams
F0i
ST-Bus
Rin/Sin
Rout/Sout
Channel 31
Channel 0
125
μ
sec
Channel 1
Channel 30
F0i
GCI interface
Note: Refer to Figures 9 and 10 for timing details
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PDF描述 |
|---|---|
| MT933 | () |
| MT93L16 | Low-Voltage Acoustic Echo Canceller(低電壓回聲消除器) |
| MTD2955V-1 | 30V N-Channel PowerTrench MOSFET |
| MTD2955V-1G | 30V N-Channel PowerTrench MOSFET |
| MTD2955VG | 30V N-Channel PowerTrench MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9300AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BL | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9300BV | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel Voice Echo Canceller |
| MT9315 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS Acoustic Echo Canceller |
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