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參數(shù)資料
| 型號： | MT91L62 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | 3 Volt Single Rail Codec(3V 單軌編解碼器) |
| 中文描述： | 3伏單鐵編解碼器（3V的單軌編解碼器） |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 79K |
| 代理商： | MT91L62 |
MT91L62
Advance Information
7-174
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
13
V
Bias
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1
μ
F capacitor to V
SS
.
Reference Voltage for Codec (Output).
Nominally [(V
DD
/2)-1.1] volts. Used internally.
Connect 0.1
μ
F capacitor to V
SS
.
PWRST
Power-up Reset.
Resets internal state of device via Schmitt Trigger input (active low).
14
V
Ref
15
16
IC
Internal Connection.
Tie externally to V
SS
for normal operation.
A/
μ
Law Selection
. CMOS level compatable input pin governs the companding law used by the
device. A-law selected when pin tied to V
DD
or
μ
-law selected when pin tied to V
SS
.
RXMute
Receive Mute.
When 1, the transmit PCM is forced to negative zero code. When 0, normal
operation. CMOS level compatable input.
17
A/
μ
18
19
TXMute
Transmit Mute.
When 1, the transmit PCM is forced to negative zero code. When 0, normal
operation. CMOS level compatable input.
20
21
22
CSL0
CSL1
CSL2
Clock Speed Select.
These pins are used to program the speed of the SSI mode as well as the
filter/codec. Refer to Table 2 for details. CMOS level compatable input.
23
D
out
Data Output.
A tri-state digital output for 8-bit wide channel data being sent to the Layer 1
device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot
defined by STB.
24
D
in
Data Input.
A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the
falling edge of BCL during the timeslot defined by STB. CMOS level compatable input.
13
STB
Data Strobe.
This input determines the 8-bit timeslot used by the device for both transmit and
receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatable
input.
14
CLOCKin
Clock (Input).
The clock provided to this input pin is used by the internal device functions.
Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin
when the bit clock is 128 kHz or 256 kHz. CMOS level compatable input.
15
V
DD
AOUT-
Positive Power Supply.
Nominally 3 volts.
16
Inverting Analog Output.
(balanced).
17
AOUT+
Non-Inverting Analog Output.
(balanced).
18
V
SS
Ain-
Ground.
Nominally 0 volts.
19
Inverting Analog Input.
No external anti-aliasing is required.
20
Ain+
Non-Inverting Analog Input.
Non-inverting input. No external anti-aliasing is required.
AIN-
VSS
AOUT +
AOUT -
VDD
CLOCKin
AIN+
VBias
VRef
PWRST
IC
RXMute
TXMute
CSL0
CSL1
CSL2
Din
Dout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
STB
A/
μ
20 PIN PDIP/SOIC/SSOP
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