參數(shù)資料
型號(hào): MT91L60AN
廠商: Mitel Networks Corporation
元件分類: Codec
英文描述: ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)
中文描述: ISO2 - CMOS三伏多功能的編解碼器(MFC)中
文件頁數(shù): 13/20頁
文件大?。?/td> 166K
代理商: MT91L60AN
Advance Information
MT91L60
7-119
DrGain
When high, the receiver driver gain is set to -6 dB, with sidetone.
When low, the receiver driver gain is set to 0 dB, with no sidetone.
Path Control
ADDRESS = 02h WRITE/READ VERIFY
Power Reset Value
XX00 0000
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DrGain
-
PDFDI
PDDR
When high, the FDI PLA and the Filter/Codec are powered down (default). When low, the FDI is active.
When high, the ear driver and Filter/Codec are powered down A (default). In addition, in ST-BUS mode, the selected
output channel is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The
output will be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver
and Filter/Codec are active if PDFDI is low.
When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the
microport is not affected. A software reset can be removed only by writing this bit low or by a PWRST. When low, the
reset condition is removed.
When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a
mute state (only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When
low the full transmit path functions normally (default).
When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a
mute state. When low the full receive path functions normally (default).
When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in
ST-BUS mode. Not used in SSI mode.
When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in
ST-BUS mode. Not used in SSI mode.
Rst
TxMute
RxMute
TxBsel
RxBsel
Control Register 1
ADDRESS = 03h WRITE/READ VERIFY
Power Reset Value
1100 0000
7
6
5
4
3
2
1
0
PDFDI PDDR
TxBsel RxBsel
Rst
_
TxMute RxMute
Note: Bits marked "-" are reserved bits and should be written with logic "0"
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