參數(shù)資料
型號: MT9174AN
廠商: Mitel Networks Corporation
英文描述: ISO2-CMOS ST-BUS⑩ FAMILY Digital Network Interface Circuit with Receive Sync Marker Bit
中文描述: ISO2 -意法半導(dǎo)體的CMOS與接收同步標(biāo)記總線⑩家庭數(shù)字網(wǎng)絡(luò)接口電路位
文件頁數(shù): 3/4頁
文件大?。?/td> 33K
代理商: MT9174AN
Advance Information
MT9174
9-157
15
17
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.
16
19
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.
Oscillator Output
. CMOS Output.
Oscillator Input
. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1’
,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When logic ’0’,
the L
OUT
to the precanceller path is enabled and functions normally. An internal
pulldown (50 k
) is provided on this pin.
No Connection.
Leave open circuit
17
19
21
22
OSC2
OSC1
20
23
Precan
18
1,6,
18,
20,
25
24
NC
21
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When
logic “0”, L
OUT
functions normally. An internal pulldown (50 k
) is provided on this pin.
Test Pin.
Connect to V
SS
.
Receive Signal
input (Analog).
Positive Power Supply
(+5V) input.
22
23
24
26
27
28
TEST
L
IN
V
DD
Pin Description (continued)
Pin #
Name
Description
24
28
相關(guān)PDF資料
PDF描述
MT9174AP ISO2-CMOS ST-BUS⑩ FAMILY Digital Network Interface Circuit with Receive Sync Marker Bit
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