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參數(shù)資料
| 型號(hào)： | MT9173AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Digital Subscriber Interface Circuit with RxSB |
| 中文描述： | 數(shù)字用戶接口電路RxSB |
| 文件頁數(shù)： | 18/22頁 |
| 文件大小： | 411K |
| 代理商： | MT9173AP |
MT9173/74
Preliminary Information
9-154
Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode
Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode
AC Electrical Characteristics
- Clock Timing - MOD Mode (Figure 18)
Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25
°
C, for design aid only: not guaranteed and not subject to production testing.
Figure 18 - RCK, TCK & CLD Timing For MOD Mode
Characteristics
Sym
80 kbit/s
160 kbit/s
Units
Test
Conditions
Min
Typ*
Max Min
Typ*
Max
1 TCK/RCK Clock Period
2 TCK/RCK Clock Width
3 TCK/RCK Clock Transition Time
4 CLD to TCK Setup Time
5 CLD to TCK Hold Time
6 CLD Width Low
7 CLD Period
t
CP
t
CW
t
CT
t
CLDS
t
CLDH
t
CLDW
t
CLDP
12.5
6.25
20
3.125
3.125
6.05
8
x
t
CP
6.25
3.125
20
1.56
1.56
2.925
8
x
t
CP
μ
s
μ
s
ns
μ
s
μ
s
μ
s
μ
s
C
L
=40pF
C4
F0
2.0V
0.8V
2.0V
0.8V
t
C4P
t
C4W
t
F0S
t
F0H
t
F0W
t
C4W
C4
OSC1
2.0V
0.8V
3.0V
2.0V
J
C
Φ
RCK
TCK
CLD
t
CT
t
CP
t
CLDS
t
CLDH
t
CW
t
CT
t
CLDW
t
CW
2.4V
0.4V
2.4V
0.4V
2.4V
0.4V
t
CP
Note 1:
TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the
DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the D
o
output
and may be skewed with respect to TCK due to end-to-end delay.
Note 2:
At the slave end TCK is phase locked to RCK.
The rising edge of TCK will lead the rising edge of RCK by approximately 90
o
.
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