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參數(shù)資料
| 型號： | MT9173AE1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB |
| 中文描述： | DATACOM, DIGITAL SLIC, PDIP24 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-24 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 613K |
| 代理商： | MT9173AE1 |
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MT9173/74
Data Sheet
8
Zarlink Semiconductor Inc.
The Transmit/Receive Timing and Control block generates all the clocks for the transmit and receive functions and
controls the entire chip according to the control register. In order that more than one DNIC may be connected to the
same DV and CD ports an F0o signal is generated which signals the next device in a daisy chain that its channel
times are now active. In this arrangement only the first DNIC in the chain receives the system F0 with the following
devices receiving its predecessor’s F0o.
In MOD mode, all the ports have a different format. The line port again operates at 80 or 160 kbit/s, however, there
is no synchronization overhead, only transparent data. The DV and CD ports carry serial data at 80 or 160 kbit/s
with the DV port transferring all the data for the line and the CD port carrying the C-channel only. In this mode the
transfer of data at both ports is synchronized to the TCK and RCK clocks for transmit and receive data, respectively.
The CLD signal goes low to indicate the start of the C-channel data on the CD port. It is used to load and latch the
input and output C-channel but has no relationship to the data on the DV port.
In DN MAS mode, the RxSB pin outputs a pulse corresponding to the position of the synchronization bit within the
received biphase data stream. Since the delay in transmission between DNICs is dependent upon line length, the
position of the RxSB pulse will vary as the line length is varied. This feature can be used to determine total loop
delay which is necessary in wireless base stations where all of the microcells need to be synchronized. In DN SLV
mode, The RxSB pin is also active although its timing is fixed and does not vary with line length. For both DN MAS
and SLV modes, the RxSB pin can be also used as a hardware SYNC indicator. In MODEM mode, for both MAS
and SLV ends, the RxSB pin is inactive and held low.
Operating Modes (MS0-2)
The logic levels
present on the mode select pins MS0, MS1 and MS2 program the DNIC for different operating
modes and configure the DV and CD ports accordingly. Table 1 shows the modes corresponding to the state of
MS0-2. These pins select the DNIC to operate as a MASTER or SLAVE, in DUAL or SINGLE port operation, in
MODEM or DIGITAL NETWORK mode and the order of the C and D channels on the CD port. Table 2 provides a
description of each mode and Table 3 gives a pin configuration according to the mode selected for all pins that have
variable functions. These functions vary depending on whether it is in MAS or SLV, and whether DN or MOD mode
is used.
Table 1 - Mode Select Pins
E=Enabled
Blanks are disabled
X=Not Applicable
Mode Select Pins
MS2
MS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Mode
Operating Mode
SINGL
E
MS0
0
1
0
1
0
1
0
1
SLV
MAS
E
E
E
E
DUAL
MOD
DN
E
D-C
E
X
C-D
ODE
E
E
E
E
E
E
E
0
1
2
3
4
5
6
7
E
E
E
E
X
E
E
E
E
E
E
X
E
E
E
E
E
E
E
E
X
E
E
E
E
E
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