參數(shù)資料
型號: MT9160BN
廠商: Mitel Networks Corporation
元件分類: Codec
英文描述: ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)
中文描述: ISO2 - 5伏的CMOS多精選編解碼器(MFC)中
文件頁數(shù): 11/28頁
文件大?。?/td> 402K
代理商: MT9160BN
Preliminary Information
MT9160
7-87
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.
PWRST/Software Reset (Rst)
While the MT9160 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing Rst logic low or by setting the PWRST pin.
After Power-up reset (PWRST) or software reset
(Rst) all control bits assume their default states;
μ
-Law functionality, usually 0 dB programmable
gains as well as the device powered up in SSI mode
2048 kb/s operation with Dout tri-stated while there
is no strobe active on STB. If a valid strobe is
supplied to STB, then Dout will be active, during the
defined channel.
To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or put PWRST pin
low.
5V Multi-featured Codec Register Map
00
RxINC
RxFG
2
RxFG
1
RxFG
0
TxINC
TxFG
2
TxFG
1
TxFG
0
Gain Control
Register 1
01
-
-
-
-
-
STG
2
STG
1
STG
0
Gain Control
Register 2
02
-
-
-
-
-
-
-
DrGain
Path Control
03
PDFDI
PDDR
RST
-
T
x
Mute
R
x
Mute
T
x
Bsel
R
x
Bsel
Control
Register 1
04
CEN
DEN
D8
A/
μ
Smag/
CCITT
CSL
2
CSL
1
CSL
0
Control
Register 2
05
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
C-Channel
Register
06
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D-Channel
Register
07
-
-
-
-
PCM/
ANALOG
loopen
-
-
Loop Back
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