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參數(shù)資料
| 型號： | MT9160AE |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| 中文描述： | ISO2 - 5伏的CMOS多精選編解碼器（MFC）中 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大小： | 402K |
| 代理商： | MT9160AE |
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MT9160
Preliminary Information
7-80
Overview
The 5V Multi-featured Codec (MFC) features
complete
Analog/Digital
conversion of audio signals (Filter/Codec) and an
analog interface to a standard handset transmitter
and receiver (Transducer Interface). The receiver
amplifier is capable of driving a 300 ohm load.
and
Digital/Analog
Each of the programmable parameters within the
functional blocks is accessed through a serial
microcontroller port compatible with Intel MCS-51
,
Motorola
SPI
and
Microwire
specifications.
include: gain control, power down, mute, B-Channel
select (ST-BUS mode), C&D channel control/access,
law control, digital interface programming and
loopback. Optionally the device may be used in a
controllerless mode utilizing the power-on default
settings.
National
Semiconductor
These
parameters
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are CCITT
G.711 A-law or
μ
-Law, with true-sign/ Alternate Digit
Inversion or true-sign/Inverted Magnitude coding,
respectively. Optionally, sign- magnitude coding may
also be selected for proprietary applications.
The Filter/Codec block also implements transmit and
receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also
included to provide proportional transmit speech
feedback to the handset receiver. This side tone path
feature is disabled by default. Figure 3 depicts the
nominal half-channel and side-tone gains for the
MT9160.
In the event of PWRST, the MT9160 defaults such
that the side-tone path is off, all programmable gains
are set to 0dB and CCITT
μ
-Law is selected. Further,
the digital port is set to SSI mode operation at 2048
kb/s and the FDI and driver sections are powered up.
(See Microport section.)
The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply
design.
continued into the Transducer Interface section to
provide full chip realization of these capabilities for
the handset functions.
This
fully
differential
architecture
is
A reference voltage (V
Ref
), for the conversion
requirements of the Codec section, and a bias
voltage (V
Bias
), for biasing the internal analog
sections, are both generated on-chip. V
Bias
is also
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1
μ
F
capacitor must be connected from V
Bias
to analog
ground at all times. Likewise, although V
Ref
may only
be used internally, a 0.1
μ
F capacitor from the V
Ref
pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
V
Ref
and V
Bias
pins are situated on adjacent pins.
The transmit filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0 dB). Gain control allows the output
signal to be increased up to 7 dB. An anti-aliasing
filter is included. This is a second order lowpass
implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0dB). Gain control allows the output
signal to be attenuated up to 7 dB. Filter response is
peaked to compensate for the sinx/x attenuation
caused by the 8 kHz sampling rate.
Side-tone is derived from the input of the Tx filter and
is not subject to the gain control of the Tx filter
section. Side-tone is summed into the receive
handset transducer driver path after the Rx filter gain
control section so that Rx gain adjustment will not
affect side-tone levels. The side-tone path may be
enabled/disabled with the gain control bits located in
Gain Control Register 2 (address 01h).
Transmit and receive filter gains are controlled by the
TxFG
0
-TxFG
2
and RxFG
0
-RxFG
2
control bits,
respectively. These are located in Gain Control
Register 1 (address 00h). Transmit filter gain is
adjustable from 0 dB to +7 dB and receive filter gain
from 0dB to -7 dB, both in 1 dB increments.
Side-tone filter gain is controlled by the STG
0
-STG
2
control bits located in Gain Control Register 2
(address 01h). Side-tone gain is adjustable from
-9.96 dB to +9.96 dB in 3.32 dB increments.
Intel and MCS-51 are registered trademarks of Intel Corporation
Motorola and SPI are registered trademarks of Motorola Corporation
National and Microwire are trademarks of National Semiconductor Corporation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9160AS | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9160BN | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT91610 | Programmable Ringing SLIC(可編程振鈴用戶線路接口電路（帶一個外部驅(qū)動器）) |
| MT9161B | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9161BE | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9160AN1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:3 Volt Multi-Featured Codec (MFC) |
| MT9160AS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT9160B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9160BE | 制造商:Microsemi Corporation 功能描述:MULTI-FEATURED CODEC 24PDIP - Rail/Tube |
| MT9160BN | 制造商:Microsemi Corporation 功能描述: |
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