參數(shù)資料
型號： MT90870
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 12 k Digital Switch (F12kDX)
中文描述： 靈活的12畝數(shù)字交換機(jī)（F12kDX）
文件頁數(shù)： 14/86頁
文件大?。?/td> 2093K
代理商： MT90870
MT90870
Data Sheet
14
Zarlink Semiconductor Inc.
BCSTo0-3
C14, A15, B15,
C15
Backplane Output Channel High Impedance Control (5 V Tolerant
Three-state Outputs).
Active high output enable which may be used to
control external buffering individually for a set of Backplane output
streams on a per channel basis.
In non-32 Mb/s mode (stream rates 2 Mb/s to 16 Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12,16,20,24,28],
BCSTo1 is the output enable for BSTo[1,5,9,13,17,21,25,29],
BCSTo2 is the output enable for BSTo[2,6,10,14,18,22,26,30],
BCSTo3 is the output enable for BSTo[3,7,11,15,19,23,27,31].
In 32 Mb/s mode (stream rate 32 Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12],
BCSTo1 is the output enable for BSTo[1,5,9,13],
BCSTo2 is the output enable for BSTo[2,6,10,14],
BCSTo3 is the output enable for BSTo[3,7,11,15].
Refer to descriptions of the
BORS
and
ODE
pins for control of the output
High or High-Impedance state.
FP8i
U14
Frame Pulse Input (5 V Tolerant).
This pin accepts the Frame Pulse
signal. The pulse width may be active for 122 ns or 244 ns at the frame
boundary and the Frame Pulse Width bit (FPW) of the Control Register
must be set Low (default) for a 122 ns and set High for a the 244 ns pulse
condition.The device will automatically detect whether an ST-BUS or GCI-
BUS style frame pulse is applied.
C8i
W12
Master Clock Input (5 V Tolerant).
This pin accepts a 8.192 MHz clock.
The internal Frame Boundary is aligned with the rising edge of this clock.
This rising edge frame boundary alignment is controlled by the C8IPOL bit
in the Control Register as shown in Table 16 on page 52. The C8IPOL bit
MUST be set to ONE for the rising edge frame boundary to be detected
correctly. Falling C8i edge frame boundary alignment is not supported
and should not be used.
CS
B11
Chip Select (5 V Tolerant).
Active low input used by the microprocessor
to enable the microprocessor port access. This input is internally set low
during a device RESET.
DS
A11
Data Strobe (5 V Tolerant).
This active low input works in conjunction
with CS to enable the microprocessor port read and write operations.
R/W
C11
Read/Write (5 V Tolerant).
This input controls the direction of the data
bus lines (D0-D15) during a microprocessor access.
A0 - A14
D5, C6, A6, D7,
C7, B7, C8, B8,
A8, D9, B9, A9,
D10, C10, A10
Address 0 - 14 (5 V Tolerant).
These pins form the 15-bit address bus to
the internal memories and registers. (Address A0 = LSB).
Pin Description (continued)
Name
Package
Coordinates
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90870AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays
MT90870AG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays
MT90871 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX)
MT90871AV 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90871AV2 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
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