- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359234 > MT90820AL (ZARLINK SEMICONDUCTOR INC) Large Digital Switch PDF資料下載
參數(shù)資料
| 型號(hào)： | MT90820AL |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Large Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP100 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC-1, MQFP-100 |
| 文件頁數(shù)： | 23/37頁 |
| 文件大?。?/td> | 573K |
| 代理商： | MT90820AL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
MT90820
Data Sheet
23
Zarlink Semiconductor Inc.
Serial Input Frame Alignment Evaluation
The MT90820 is capable of performing frame alignment evaluation. The frame pulse under evaluation is connected
to the FE (frame measurement) pin. An external multiplexer is required to selected one of the frame pulses related
to the different input streams. Figure 6 gives an example of performing measurement for 16 frame pulses can be
performed.
Figure 5 - Switch Matrix with Serial Stream at Various Bit Rates
Figure 6 - Serial Input Frame Alignment Evaluation for Various Frame Pulses
Wide Frame Pulse (WFP) Frame Alignment Mode
When the device is the wide frame pulse mode, the device can operate in the HMVIP and MVIP-90 environment if
the input data streams are sampled at 3/4 bit time. When input data stream are sampled at half-bit time as specified
in the HMVIP and MVIP-90 standard, the device can only operate with data rate of 2 Mb/s. Refer to the ST-BUS
output delay parameter, t
SOD
, as specified in the AC Electrical Characteristic table.
16 Streams
IN
16 Streams
OUT
16 Streams
16 Streams
MT90820
#1
MT90820
#2
MT90820
#3
MT90820
#4
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
1,024 - Channel Switch
2,048 - Channel Switch
4,096 - Channel Switch
Bit Rate
(IN/OUT)
Size of
Switch Matrix
STi0
STi1
STi2
STo[0:15]
STi15
Frame Alignment
Evaluation circuit
Central
Timing Source
FE
input
CLK
FP
FP STi15
FP STi0
FP STi1
FP STi2
External
Mux
MT90820
Note:
1. Use the external mux to select one of the serial frame pulses.
2. To start a measurement cycle, set the Start Frame Evaluation (SFE) bit in the IMS register low for at least 1 frame.
3. Frame evaluation starts when the SFE bit is changed from low to high.
4. Two frames later, the Complete Frame Evaluation (CFE) bit of the Frame Alignment Register (FAR) changes from low to high to
signal the CPU that a valid offset measurement is ready to be read from bit [11:0] of the FAR register.
5. The SFE bit must be set to zero before a new measurement cycle started.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90820AL1 | Large Digital Switch |
| MT90823AL1 | 3V Large Digital Switch |
| MT90823 | 3V Large Digital Switch |
| MT90823AB | 3V Large Digital Switch |
| MT90823AG | 3V Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90820AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100MQFP |
| MT90820AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820AP1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
| MT90820APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 5V 84PLCC - Tape and Reel |
| MT90820APR1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。