參數(shù)資料
型號： MT90820
廠商： Zarlink Semiconductor Inc.
英文描述： Large Digital Switch
中文描述： 大型數(shù)字開關(guān)
文件頁數(shù)： 20/37頁
文件大?。?/td> 573K
代理商： MT90820
MT90820
Data Sheet
20
Zarlink Semiconductor Inc.
Test Access Port (TAP)
The Test Access Port (TAP) provides access to the many test functions of the MT90820. It consists of three input
pins and one output pin. The following pins are from the TAP.
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain
independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
Vdd when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VDD.
Instruction Register
In accordance with the IEEE 1149.1 standard, the MT90820 uses public instructions. The MT90820 JTAG Interface
contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when
the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic
functions: to select the test data register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and DO during data register scanning.
Test Data Register
As specified in IEEE 1149.1, the MT90820 JTAG Interface contains two test data registers:
The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT90820 core logic.
The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO.
The MT90820 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit
clocked out. All tristate enable bits are active high.
相關(guān)PDF資料
PDF描述
MT90820AL Large Digital Switch
MT90820AL1 Large Digital Switch
MT90823AL1 3V Large Digital Switch
MT90823 3V Large Digital Switch
MT90823AB 3V Large Digital Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90820AL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays
MT90820AL1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 131.072MBPS 5V 100MQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100MQFP
MT90820AP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch
MT90820AP1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Large Digital Switch
MT90820APR 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 5V 84PLCC - Tape and Reel
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