- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383645 > MT9075 (Mitel Networks Corporation) () PDF資料下載
參數(shù)資料
| 型號： | MT9075 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 95K |
| 代理商： | MT9075 |
MSAN-174
Application Note
8
The MT9075 contains an adaptive microport that can
easily interface to Intel or Motorola non-multiplexed
processors. Figure 6 shows how MT9075 works with
some of the most popular microprocessors, such as
MC68302 or 8052.
As a mixed analog and digital signal device, the
MT9075 has separate sets of power supply. It is
recommended that in layout, the user shall run
separate connections for digital power/ground and
analog power/ground to maximize the noise
immunity. Proper decoupling on the power rails is
also important.
3.2 Timing and synchronization control
In any digital transmission system the timing and
synchronization are critical for proper functioning of
the communication link. The AN is responsible for
synchronizing itself to the LE, supplying clocks to the
subscriber modules and attenuating jitter.
As the gateway to a local exchange, the AN must
extract the timing from one of the E1 links. The
system clocks of the AN need to be phase locked to
this extracted timing signal.
Figure 5a showed how MT9075 in Line Synchronous
mode is capable of deriving the reference signal by
which the jitter attenuated system clocks can be
generated. If the reference clock is lost due to the
link failure, reference switching occurs. In this case,
advanced phase lock loop (PLL) switches its locking
from the current reference to another when the
current reference is lost or impaired. Using this
scheme, synchronization is constantly maintained
even when E1 links in V5.2 (or multiple V5.1) fail.
Using a PLL capable of reference switching
simplifies the implementation of the protection
protocol specified in the V5 interface.
The reference switching scheme is implemented by
MT9042B, a multitrunk system synchronizer that
accepts reference inputs from two independent
sources, the PRI and the SEC. As shown in Figure
5b, each E1 interface circuit extracts a reference
clock from its own link and feed it into two MUXs.
The two MUXs, controlled by the system controller,
determine which reference clock will be selected as
PRI and SEC respectively. For example, if the
MT9042B is locked to PRI, but during the course of
operation the PRI signal is lost, MT9042B can
potentially switch the reference from PRI to SEC
automatically (when in automatic mode) or under the
supervision of the system controller in manual mode.
The reference switching performed by the MT9042B
is bit error free, meaning that the phase difference
between PRI and SEC will be absorbed by the
device. Hence no jitter is added to output clocks and
the reference switching also takes into consideration
the
Maximum
Time
requirements.
Interval
Error
(MTIE)
In addition to the 8KHz frame pulse and 4MHz clock
needed by MT9075, the MT9042B also provides
1.544MHz, 2.048MHz, 3.088MHz, 8.192MHz and
16.384MHz output clocks.
The above reference switching solution is also
applicable when more than one V5.1 interfaces are
implemented in an AN.
3.3 Switching matrix
As the core of the AN, the switching matrix is
responsible
for
routing,
broadcasting any type of data, including bearer
channels, C-channels, or other message channels.
The switch also serves as a part of the V5 protection
protocol, re-routing the logical C-channel onto any
available physical C-channel during a link failure in
order to maintain service.
concentrating
and
The size of the matrix depends on how many
2.048Mb/s links will be used in the V5.2 interface, as
well as the concentration ratio. When all 16 links are
deployed, a minimum 512 by 512 switch is required.
If a 4:1 concentration is decided, the matrix must be
expanded to 2048 by 512.
Mitel offers a wide range of digital switches to suit
various applications. The available modules range
from 64 by 64 up to 2048 by 2048 non-blocking
matrices,which form the basis for any larger size or
blocking matrix. The 256 by 256 MT8985 and the
2048 by 2048 MT90820 are suggested for V5.1 and
V5.2 applications, respectively. Both switches feature
the frame integrity and message mode. Using
constant delay, a user can transport hyperchannel
(Nx64Kb/s) data through the AN. Message mode
gives the user direct access to the content of any
timeslot of any 2.048Mb/s data stream.
The MT90820 is uniquely capable of measuring and
then compensating the cable delay of the 16 input
streams when a skew exists between the frame
pulses. The MT90820 also has a per-channel
loopback feature, which allows the data on any
output channel to be looped back internally to the
input channel for diagnostic purpose. This gives the
user a convenient way to do on-line testing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076AB | T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| MT9079 | Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器) |
| MT9080B | SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9075A | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:E1 Single Chip Transceiver |
| MT9075B-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。