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參數(shù)資料
| 型號： | MT90733AP |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 52K |
| 代理商： | MT90733AP |
Advance Information
CMOS
MT90733
5-27
Note: I = Input; O = Output; P = Power
Note: I = Input; O = Output; P = Power
Other Signals
Pin #
Name
I/O/P
Description
7
TEST
I
Test Pin:
Leave open.
9
OENA
O
Overhead Enable.
An active high signal that enables an overhead error to be
introduced into the overhead bit in the next 85th group by placing a low on the
FORCEOE lead.
11
X1
O
DS3 Received X-Bit 1.
An output indication of the state of the first X-bit
received in the DS3 frame.
13
X2
O
DS3 Received X-Bit 2.
An output indication of the state of the second X-bit
received in the DS3 frame (bit 680).
15
STUFD
O
Stuff Data Status.
This output signal provides an indication of the state of the
stuff opportunity bit from the received DS3F frame.
16
STUFC
O
Stuff Clock.
Provided for clocking out the stuff opportunity bit state.
43
FE
O
Framing Error Indication.
An active high signal is generated when a framing
error is detected while in frame alignment. The framing error indication is held
active low when a DS3 out of frame alarm occurs.
49
TFIN
I
Optional Framing Input Pulse.
Not required for normal operation.
54
FORCEOE
I
Force DS3 Overhead Bit Error.
An active low input signal used in conjunction
with the overhead enable signal (OENA) for introducing an overhead bit error
in the next transmitted 85-bit group.
55
FORCEPP
I
Force P-Bit Parity Error.
An active low input signal generates and transmits a
P-bit error by inverting both P-bits.
57
FORCECP
I
Force C-Bit Parity Error.
An active low input signal generates and transmits a
C-bit parity error when operating in the C-bit parity mode.
61
FORCFEBE
I
Force FEBE Error.
An active low input signal generates and transmits a far
end block error (FEBE) when operating in the C-bit parity mode.
Microprocesssor Interface
Pin #
Name
I/O/P
Description
8
SEL
I
Microprocessor Select.
A low enables the processor to access the DS3F
memory map for control, status and alarm information.
10
ALE
I
Address Latch Enable.
An active high input signal is used by the processor
to hold an address stable during a read/write bus cycle on the falling edge.
12
RD
I
Read.
An active low input signal generated by the processor for reading the
registers which reside in the DS3F memory map.
14
WR
I
Write.
An active low input signal generated by the processor for writing to the
registers which reside in the memory map.
18-21
23-26
AD(7-4)
AD(3-0))
I/O
Address/Data Bus.
These leads constitute the time multiplexed address and
data bus for accessing the registers which reside in the DS3F memory map.
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