
Preliminary Information
MT90502
5
C9
1. rxa_clav
2. rxa_enb
rxa_d[7:0]
1. UTOPIA port A RX Cell Available (in ATM)
2. UTOPIA port A RX Enable (in PHY)
UTOPIA port A RX Data bus
A12, C11,
B11, A11,
D10, C10,
B10, A10
B12
D17
C17
B17
D5
D8
A6
rxa_prty
txb_led
rxb_led
rxb_alarm
txb_clk
txb_soc
1. txb_enb
2. txb_clav
1. txb_clav
2. txb_enb
txb_d[7:0]
UTOPIA port A RX Parity
UTOPIA port B TX LED
UTOPIA port B RX LED
UTOPIA port B PHY alarm
UTOPIA port B TX clock
UTOPIA port B TX Start of Cell
1. UTOPIA port B TX Enable (in ATM)
2. UTOPIA port B TX Cell Available (in PHY)
1. UTOPIA port B TX Cell Available (in ATM)
2. UTOPIA port B TX Enable (in PHY)
UTOPIA port B TX Data bus
B6
B8, A8, D7,
C7, B7, A7,
D6, C6
C8
E4
A4
txb_prty
rxb_clk
rxb_soc
txa_addr[4]
1. rxb_enb
2. rxb_clav
1. rxb_clav
2. rxb_enb
rxb_d[4:0]
rxa_addr[4:0]
rxb_d[7:5]
txa_addr[2:0]
rxb_prty
txa_addr[3]
txc_clk
txc_soc
1. txc_enb
2. txc_clav
1. txc_clav
2. txc_enb
txc_d[7:0]
UTOPIA port B TX Parity
UTOPIA port B RX clock
UTOPIA port B RX Start of Cell. txa_addr[4] when UTOPIA is configured as single
PHY port.
1. UTOPIA port B RX Enable (in ATM)
2. UTOPIA port B RX Cell Available (in PHY)
1. UTOPIA port B RX Cell Available (in ATM)
2. UTOPIA port B RX Enable (in PHY)
UTOPIA port B RX Data bus [4:0]. rxa_addr[4:0] when UTOPIA is configured as
single PHY port.
UTOPIA port B RX Data bus [7:5]. txa_addr[2:0] when UTOPIA is configured as
single PHY port.
UTOPIA port B RX Parity. txa_addr[3] when UTOPIA is configured as single PHY
port.
UTOPIA port C TX clock
UTOPIA port C TX Start of Cell
1. UTOPIA port C TX Enable (in ATM)
2. UTOPIA port C TX Cell Available (in PHY)
1. UTOPIA port C TX Cell Available (in ATM)
2. UTOPIA port C TX Enable (in PHY)
UTOPIA port C TX Data bus
D3
C1
A2, D4, A1,
B1, C2
A3, B3, B2
B4
J4
D2
G1
G2
E3, E2, E1,
F3, F2, F1,
G4, G3
D1
L1
H3
txc_prty
rxc_clk
rxc_soc
UTOPIA port C TX Parity
UTOPIA port C RX clock
UTOPIA port C RX Start of Cell
Pin Description (continued)
EPBGA Pin
Name
Description (see notes 1-8)