參數(shù)資料
型號： MT9042C
廠商： Mitel Networks Corporation
英文描述： Multitrunk System Synchronizer
中文描述： Multitrunk系統(tǒng)同步
文件頁數(shù)： 6/28頁
文件大?。?/td> 113K
代理商： MT9042C
MT9042C
Advance Information
6
Digitally Controlled Oscillator (DCO) - the DCO
receives the limited and filtered signal from the Loop
FIlter, and based on its value, generates a
corresponding
digital
synchronization method of the DCO is dependent on
the state of the MT9042C.
output
signal.
The
In Normal Mode, the DCO provides an output signal
which is frequency and phase locked to the selected
input reference signal.
In Holdover Mode, the DCO is free running at a
frequency equal to the last (less 30ms to 60ms)
frequency the DCO was generating while in Normal
Mode.
In Freerun Mode, the DCO is free running with an
accuracy equal to the accuracy of the OSCi 20MHz
source.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output
Interface Circuit to provide the output signals shown
in Figure 5. The Output Interface Circuit uses two
Tapped Delay Lines followed by a T1 Divider Circuit
and an E1 Divider Circuit to generate the required
output signals.
Figure 5 - Output Interface Circuit Block
Diagram
Two tapped delay lines are used to generate a
16.384MHz signal and a 12.352MHz signal.
The E1 Divider Circuit uses the 16.384MHz signal to
generate four clock outputs and three frame pulse
outputs. The C8o, C4o and C2o clocks are
generated by simply dividing the C16o clock by two,
four and eight respectively. These outputs have a
nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to
generate two clock outputs. C1.5o and C3o are
generated by dividing the internal C12 clock by four
and eight respectively. These outputs have a
nominal 50% duty cycle.
The frame pulse outputs (F0o, F8o, F16o) are
generated directly from the C16 clock.
The T1 and E1 signals are generated from a
common DPLL signal. Consequently, the clock
outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o and
F16o are locked to one another for all operating
states, and are also locked to the selected input
reference in Normal Mode. See Figures 20 & 21.
All frame pulse and clock outputs have limited driving
capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and
automatically
enables
(Auto-Holdover) when the frequency of the incoming
signal is outside the auto-holdover capture range (See
AC Electrical Characteristics - Performance). This
includes a complete loss of incoming signal, or a large
frequency shift in the incoming signal. When the
incoming signal returns to normal, the DPLL is
returned to Normal Mode with the output signal locked
to the input signal. The holdover output signal is
based on the incoming signal 30ms minimum to 60ms
prior to entering the Holdover Mode. The amount of
phase drift while in holdover is negligible because the
Holdover Mode is very accurate (e.g.,
±
0.05ppm). The
the Auto-Holdover circuit does not use TIE correction.
Consequently, the phase delay between the input and
output after switching back to Normal Mode is
preserved (is the same as just prior to the switch to
Auto-Holdover).
the
Holdover
Mode
Automatic/Manual Control State Machine
The Automatic/Manual Control State Machine allows
the MT9042C to be controlled automatically (i.e.,
LOS1, LOS2 and GTi signals) or controlled manually
(i.e., MS1, MS2, GTi and RSEL signals). With
manual control a single mode of operation (i.e.,
Normal, Holdover and Freerun) is selected. Under
automatic control the state of the LOS1, LOS2 and
GTi signals determines the sequence of modes that
the MT9042C will follow.
As shown in Figure 1, this state machine controls the
Reference Select MUX, the TIE Corrector Circuit, the
Tapped
Delay
Line
From
DPLL
Tapped
Delay
Line
T1 Divider
E1 Divider
16MHz
12MHz
C3o
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
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參數(shù)描述
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MT9043AN 制造商:Microsemi Corporation 功能描述:
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