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| 型號： | MT8LDT864HX |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SMALL-OUTLINE DRAM MODULE |
| 中文描述： | 小外形DRAM模塊 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 625K |
| 代理商： | MT8LDT864HX |
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4, 8 Meg x 64 DRAM SODIMMs
DM83.p65
–
Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
15
4, 8 MEG x 64
DRAM SODIMMs
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
3. I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100μs is required after power-
up, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
t
REF refresh requirement is exceeded.
7. AC characteristics assume
t
T = 5ns for FPM and
t
T = 2.5ns for EDO.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate
specification, all input signals must transit between
V
IH
and V
IL
(or between V
IL
and V
IH
) in a mono-
tonic manner.
10.If CAS# = V
IH
, data output is High-Z.
11.If CAS# = V
IL
, data output may contain data from
the last valid READ cycle.
12.Measured with a load equivalent to two TTL gates
and 100pF and V
OL
= 0.8V and V
OH
= 2V.
13.If CAS# is LOW at the falling edge of RAS#, Q will
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
t
CP.
14.The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively
by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD (MAX) limit,
t
AA and
t
CAC
must always be met.
15.The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively
by
t
AA (
t
RAC and
t
CAC no longer applied). With
or without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC must always be met.
16.Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
18.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
19.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
Additionally, with EDO, WE# must be pulsed
during CAS# HIGH time in order to place I/O
buffers in High-Z.
20.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The 3ns minimum is a parameter guaranteed by
design.
22.Column address changed once each cycle.
23.8MB module values will be half of those shown.
24.With the FPM option,
t
OFF is determined by the
first RAS# or CAS# signal to transition HIGH. In
comparison,
t
OFF on an EDO option is deter-
mined by the latter of the RAS# and CAS# signals
to transition HIGH.
25.Applies to both FPM and EDO operating modes.
26.All other inputs at 0.2V or V
DD
- 0.2V.
27.
t
WCS,
t
RWD,
t
AWD and
t
CWD are not restrictive
operating parameters.
t
WCS applies to EARLY
WRITE cycles.
t
RWD,
t
AWD and
t
CWD apply to
READ-MODIFY-WRITE cycles. If
t
WCS
≥
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit through-
out the entire cycle. If
t
WCS <
t
WCS (MIN) and
t
RWD
≥
t
RWD (MIN),
t
AWD
≥
t
AWD (MIN) and
t
CWD
≥
t
CWD (MIN), the cycle is a READ-
MODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW result in a LATE
WRITE (OE#-controlled) cycle.
t
WCS,
t
RWD,
t
CWD and
t
AWD are not applicable in a LATE
WRITE cycle.
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