參數(shù)資料
型號(hào)： MT8LD864AG-5X
廠商： Micron Technology, Inc.
英文描述： DRAM MODULE
中文描述： DRAM模塊
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 518K
代理商： MT8LD864AG-5X
7
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65
–
Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SPD A CKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and
its slave address. If both the device and a write opera-
tion have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions
(Figures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
Figure 3
Acknow ledge Response From Receiver
Figure 1
Data Validity
Figure 2
Definition of Start and Stop
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
SCL
SDA
START
BIT
STOP
BIT
相關(guān)PDF資料
PDF描述
MT32LD3264A Silver Mica Capacitor; Capacitance:6800pF; Capacitance Tolerance: 5%; Series:CDV30; Voltage Rating:1000VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:11.1mm; Leaded Process Compatible:No RoHS Compliant: No
MT32LD3264AG-5X Silver Mica Capacitor; Capacitance:8200pF; Capacitance Tolerance:+/- 5%; Series:CDV30; Voltage Rating:1000VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:11.1mm; Leaded Process Compatible:No RoHS Compliant: No
MT32LD3264AG-6X Silver Mica Capacitor; Capacitance:1000pF; Capacitance Tolerance:+/- 5%; Series:CDV30; Voltage Rating:1500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:11.1mm; Leaded Process Compatible:No RoHS Compliant: No
MT16LSDT1664A 8,16 MEG x 64 SDRAM DIMMs
MT16LSDT864AG-10C 8,16 MEG x 64 SDRAM DIMMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8LD864AG-6X 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM MODULE
MT8LDT264G-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 Fast Page Mode DRAM Module
MT8LDT264G-6S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 Fast Page Mode DRAM Module
MT8LDT264G-6X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 EDO Page Mode DRAM Module
MT8LDT264G-6XS 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 EDO Page Mode DRAM Module
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*