參數(shù)資料
型號(hào)： MT8LD864A
廠商： Micron Technology, Inc.
英文描述： DRAM MODULE
中文描述： DRAM模塊
文件頁(yè)數(shù)： 14/27頁(yè)
文件大?。?/td> 518K
代理商： MT8LD864A
14
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65
–
Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
19.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
20.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The maximum current ratings are based with the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half when used in the x32
mode.
22.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
23.
t
WCS,
t
RWD,
t
AWD
and
t
CWD
are
not
restrictive
operating
parameters.
t
WCS
applies
to
EARLY
WRITE
cycles.
If
t
WCS
>
t
WCS
(MIN),
the
cycle
is
an
EARLY
WRITE
cycle
and
the
data
output
will
remain
an
open
circuit
throughout
the
entire
cycle.
t
RWD,
t
AWD
and
t
CWD
define
READ-
MODIFY-WRITE
cycles.
Meeting
these
limits
allows
for
reading
and
disabling
output
data
and
then
applying
input
data.
OE#
held
HIGH
and
WE#
taken
LOW
after
CAS#
goes
LOW
result
in
a
LATE
WRITE
(OE#-controlled)
cycle.
t
WCS,
t
RWD,
t
CWD
and
t
AWD
are
not
applicable
in
a
LATE
WRITE
cycle.
24.Column address changed once each cycle.
25.The 3ns minimum parameter guaranteed by
design.
26.Measured with the specified current load and
100pF.
27.
t
OFF on an EDO module is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
28.The SPD EEPROM WRITE cycle time (
t
WR) is the
time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit are disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
29.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
possible.
30. V
IH
overshoot: V
IH
(MAX) = V
DD
+ 2V for a pulse
width
≤
10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
≤
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
3. I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100μs is required after power-
up, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
t
REF refresh requirement is exceeded.
7. AC characteristics assume
t
T = 2ns for -5 and 2.5ns
for -6.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate
specification, all input signals must transit between
V
IH
and V
IL
(or between V
IL
and V
IH
) in a mono-
tonic manner.
10.If CAS# and RAS# = V
IH
, data output is High-Z.
11.If CAS# = V
IL
, data output may contain data from
the last valid READ cycle.
12.Measured with a load equivalent to two TTL gates
and 100pF and V
OL
= 0.8V and V
OH
= 2V.
13.Requires that
t
AA and
t
CAC are not violated.
14.Requires that
t
AA and
t
RAC are not violated.
15.If CAS# is LOW at the falling edge of RAS#,
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for
t
CP.
16.The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively
by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD (MAX) limit,
t
AA and
t
CAC
must always be met.
17.The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively
by
t
AA (
t
RAC and
t
CAC no longer applied). With
or without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC must always be met.
18.Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
相關(guān)PDF資料
PDF描述
MT8LD864AG-5X DRAM MODULE
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