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參數資料
| 型號： | MT8979 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 4/26頁 |
| 文件大?。?/td> | 340K |
| 代理商： | MT8979 |
MT8979
ISO-CMOS
4-164
Functional Description
The MT8979 is a CEPT trunk digital link interface
conforming to CCITT Recommendation G.704 for
PCM 30 and I.431 for ISDN. It includes features
such as: insertion and detection of synchronization
patterns, optional cyclical redundancy check and far
end error performance reporting, HDB3 decoding
and optional coding, channel associated or common
channel signalling, programmable digital attenuation
and a two frame received elastic buffer. The
MT8979 can also monitor several conditions on the
CEPT digital trunk, which include, frame and
multiframe synchronization, received all 1’s alarms,
data slips as well as framing and CRC errors, both
near and far end.
The system interface to the MT8979 is a TDM bus
structure that operates at 2048 kbit/s known as the
ST-BUS. This serial stream is divided into 125
μ
s
frames that are made up of 32 x 8 bit channels.
The line interface to the MT8979 consists of split
phase unipolar inputs and outputs which are
supplied from/to a bipolar line receiver/driver,
respectively.
CEPT Interface
The CEPT frame format consists of 32, 8 bit
timeslots. Of the 32 timeslots in a frame, 30 are
defined as information channels, timeslots 1-15 and
17-31 which correspond to telephone channels 1-30.
An additional voice/data channel may be obtained by
placing the device in common channel signalling
mode. This allows use of timeslot 16 for 64 kbit/s
common channel signalling.
Synchronization is included within the CEPT bit
stream in the form of a bit pattern inserted into
timeslot 0. The contents of timeslot 0 alternate
between the frame alignment pattern and the
non-frame alignment pattern as described in Figure
4. Bit 1 of the frame alignment and non-frame
alignment bytes have provisions for additional
protection against false synchronization or enhanced
error monitoring. This is described in more detail in
the following section.
In order to accomplish multiframe synchronization, a
16 frame multiframe is defined by sending four zeros
in the high order quartet of timeslot 16 frame 0, i.e.,
once every 16 frames (see Figure 5). The CEPT
format has four signalling bits, A, B, C and D.
Signalling bits for all 30 information channels are
transmitted in timeslot 16 of frames 1 to 15. These
timeslots are subdivided into two quartets (see Table
6).
Cyclic Redundancy Check (CRC)
An optional cyclic redundancy check (CRC) has
been incorporated within CEPT bit stream to provide
additional protection against simulation of the frame
alignment signal, and/or where there is a need for an
enhanced error monitoring capability. The CRC
process treats the binary string of ones and zeros
contained in a submultiframe (with CRC bits set to
binary zero) as a single long binary number. This
string of data is first multiplied by x
4
then divided by
the generating polynomial x
4
+x+1. This division
process takes place at both the transmitter and
receiver end of the link. The remainder calculated at
the receiver is compared to the one received with the
data over the link. If they are the same, it is of high
probability that the previous submultiframe was
received error free.
The CRC procedure is based on a 16 frame
multiframe, which is divided into two 8 frame
submultiframes (SMF). The frames which contain
the frame alignment pattern contain the CRC bits, C
1
to C
4
respectively, in the bit 1 position. The frames
Figure 3 - CEPT Link Frame & Multiframe Format
Frame
15
0
14
15
0
Timeslot
0
1
30
31
Most
Significant
Bit (First)
Least
Significant
Bit (Last)
Bit
1
2
3
4
5
6
7
8
Frame
Frame
Frame
Frame
Timeslot
Timeslot
Timeslot
Bit
Bit
Bit
Bit
Bit
Bit
Bit
2.0 ms
(8/2.048)
μ
s
125
μ
s
相關PDF資料 |
PDF描述 |
|---|---|
| MT8979AE | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8979AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8979AC | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8980D | Digital Switch(數字開關（在微處理器控制下，轉換PCM編碼控制的話音或數據）) |
| MT8980 | ISO-CMOS ST-BUS⑩ FAMILY Digital Switch |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MT8979AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface |
| MT8979AE | 制造商:Microsemi Corporation 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8979AE1 | 制造商:Microsemi Corporation 功能描述:FRAMER CRC-4/PCM 30 5V 28PDIP - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER CRC-4/PCM 30 5V 28PDIP - Rail/Tube |
| MT8979AP | 制造商:MITEL 功能描述: |
| MT8979AP1 | 制造商:Microsemi Corporation 功能描述:FRAMER CRC-4/PCM 30 5V 44PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC FRAMER/INTERFACE CEPT 44PLCC 制造商:Microsemi Corporation 功能描述:IC FRAMER/INTERFACE CEPT 44PLCC |
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