- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383643 > MT8979 (Mitel Networks Corporation) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT8979 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 6/30頁 |
| 文件大小： | 190K |
| 代理商： | MT8979 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
MT8979
ISO-CMOS
4-92
Control Input 0 (CSTi0)
All the necessary control and signalling information
is input through the two control streams. Control
ST-BUS input number 0 (CSTi0) contains the control
information that is associated with each information
channel. Each control channel contains the per
channel digital attenuation information, the individual
loopback control bit, and the voice or data channel
identifier, see Table 2. When a channel is in data
mode (B7 is high) the digital attenuation and
Alternate Digit Inversion are disabled. It should be
noted that the control word for a given information
channel is input one timeslot early, i.e., channel 0 of
CSTi0 controls channel 1 of DSTi. Channels 15 and
31 of CSTi0 contain Master Control Words 1 and 2,
which are used to set up the interface feature as
seen by the respective bit functions of Tables 3 and
4.
Control Input 1 (CSTi1)
Control ST-BUS input stream number 1 (CSTi1)
contains the synchronization information and the A,
B, C & D signalling bits for insertion into timeslot 16
of the CEPT stream (refer to Tables 5 to 8). Timeslot
0 contains the four zeros of the multiframe alignment
signal plus the XYXX bits (see Figure 5). Channels 1
to 15 of CSTi1 contain the A, B, C & D signalling bits
as defined by the CEPT format (see Figure 5), i.e.,
channel 1 of CSTi1 contains the A,B,C & D bits for
DSTi timeslots 1 and 17. Channel 16 contains the
frame alignment signal, and channel 17 contains the
non-frame alignment signal (see Figure 4). Channel
18 contains the Master Control Word 3 (see Table 9).
Figure 11 shows the relationship between the control
stream (CSTi1) and the CEPT stream.
Control Output (CSTo)
Control ST-BUS output (CSTo) contains the
multiframe signal from timeslot 16 of frame 0 (see
Table 10). Signalling bits A, B, C & D for each CEPT
channel are sourced from timeslot 16 of frames 1-15
and are output in channels 1-15 on CSTo , as shown
in Table 11. The frame alignment signal and
nonframe alignment signal, received from timeslot 0
of alternate frames, are output in timeslots 16 and 17
as shown in Tables 12 and 13.
Channel 18 contains a Master Status Word, which
provides to the user information needed to determine
the operating condition of the CEPT interface i.e.,
frame synchronization, multiframe synchronization,
frame alignment byte errors, slips, alarms, and the
logic of the external status pin (see Table 14). Figure
12, shows the relationship between the control
stream channels and the CEPT signalling channels
in the multiframe. The ERR bit in the Master Status
word is an indicator of the number of errored frame
alignment bytes that have been received in alternate
timeslot zero. The time interval between toggles of
Figure 6 - CRC Bit Allocation and Submultiframing
Note 1 : Remote Alarm. Keep at 0 for normal operation.
Note 2 : Reserved for National use. Keep at 1 for normal operation.
Note 3 : Used to monitor far-end CRC error performance.
Multiple Frame
Component
Frame Type
CRC
Frame #
Timeslot Zero
1
2
3
4
5
6
7
8
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
Frame Alignment Signal
Non-Frame Alignment Signal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C
1
0
C
2
0
C
3
1
C
4
0
C
1
1
C
2
1
C
3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
0
A
(1)
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
0
Sn
(2)
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
1
Sn
(2)
S
M
F
I
S
M
F
I
I
Si1
(3)
C
4
Si2
(3)
indicates position of CRC-4
multiframe alignment signal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8979 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8979AE | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8979AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8979AC | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8980D | Digital Switch(數(shù)字開關(guān)（在微處理器控制下，轉(zhuǎn)換PCM編碼控制的話音或數(shù)據(jù)）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8979AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface |
| MT8979AE | 制造商:Microsemi Corporation 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8979AE1 | 制造商:Microsemi Corporation 功能描述:FRAMER CRC-4/PCM 30 5V 28PDIP - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER CRC-4/PCM 30 5V 28PDIP - Rail/Tube |
| MT8979AP | 制造商:MITEL 功能描述: |
| MT8979AP1 | 制造商:Microsemi Corporation 功能描述:FRAMER CRC-4/PCM 30 5V 44PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC FRAMER/INTERFACE CEPT 44PLCC 制造商:Microsemi Corporation 功能描述:IC FRAMER/INTERFACE CEPT 44PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。