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參數(shù)資料
| 型號(hào)： | MT8976 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MT8976 |
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4-42
MT8976
ISO-CMOS
Figure 8 - Off-Line Framer State Diagram
Hunt Mode
False Candidate
False
Candidate
Forced
Reframe
Out of
Sync.
False
Candidate
Candidate
Candidate
CRC
Check
In sync
Candidate
*
Candidate
Valid Candidate
Resync
Receiver
Valid Candidate
New Frame Position
* Note: Only when in ESF mode and CRC
option is enabled.
Maintenance
Verify
pointer and the ST-BUS read pointer will begin to
decrease over time. When this delay approaches the
minimum two channel threshold, the buffer will
perform a controlled slip, which will reset the internal
ST-BUS read pointers so that there is exactly 34
channels delay between the two pointers. This will
result in some
ST-BUS
information output in the previous frame. Repetition
of up to one DS1 frame of information is possible.
channels
containing
Conversely, if the data on the DS1 side is being
written into the buffer at a rate faster than that at
which it is being read out on the ST-BUS side, the
delay between the DS1 frame and the ST-BUS frame
will increase over time. A controlled slip will be
performed when the throughput delay exceeds 42
ST-BUS channels. This slip will reset the internal ST-
BUS counters so that there is a 10 channel delay
between the DS1 write pointer and the ST-BUS read
pointer, resulting in loss of up to one frame of
received DS1 data.
Note that when the device performs a controlled slip,
the ST-BUS address pointers are repositioned so
that there is either a 10 channel or a 34 channel
delay between the input DS1 frame and the output
ST-BUS frame. Since the buffer performs a
controlled slip only if the delay exceeds 42 channels
or is less than 2 channels, there is an 8 channel
hysteresis built into the slip mechanism. The device
can, therefore, absorb 8 channels or 32.5μs of jitter
in the received signal.
There is no loss of frame sync, multiframe sync or
any errors in the signalling bits when the device
performs a slip. The information on the FDL pins in
ESF or SLC-96 mode will, however, undergo slips at
the same time.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8976AC | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8976AE | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8976AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8977 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT8977 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8976AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY T1/ESF Framer Circuit |
| MT8976AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY T1/ESF Framer Circuit |
| MT8976AE1 | 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8976AP | 制造商:MITEL 功能描述: |
| MT8976AP1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: 制造商:ZARLINK 功能描述: |
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