![](http://datasheet.mmic.net.cn/370000/MT8971B_datasheet_16723769/MT8971B_2.png)
MT8971B/72B
9-108
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
DIP PLCC
1
2
3
2
3
4
L
OUT
V
Bias
V
Ref
Line Out.
Transmit Signal
output (Analog). Referenced to V
Bias
.
Internal Bias Voltage
output. Connect via 0.33 μF decoupling capacitor to V
DD
.
Internal Reference Voltage
output. Connect via 0.33 μF decoupling capacitor to V
DD
.
MS2-MS0
Mode Select
inputs (Digital). The logic levels present on these pins select the various
operating modes for a particular application. See Table 1 for the operating modes.
RegC
Regulator Control
output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
F0/CLD
Frame Pulse/C-Channel Load
(Digital). In DN mode a 244 ns wide negative pulse input
for the MASTER indicating the start of the active channel times of the device. Output for
the SLAVE indicating the start of the active channel times of the device. Output in MOD
mode providing a pulse indicating the start of the C-channel.
CDSTi/
CDi
signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate
selected.
CDSTo/
CDo
signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate
selected.
V
SS
Negative Power Supply
(0V).
DSTo/Do
Data ST-BUS Out/Data Out
(Digital). A 2.048 Mbit/s serial PCM/data output in DN mode.
In MOD mode this is a continuous bit stream at the bit rate selected.
DSTi/Di
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In
MOD mode this is a continuous bit stream at the bit rate selected.
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns wide
negative pulse indicating the end of the active channel times of the device to allow daisy
chaining. In MOD mode provides the receive bit rate clock to the system.
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.
OSC2
Oscillator Output
. CMOS Output.
4,5,
6
7
5,7,
8
9
8
10
9
12
Control/Data ST-BUS In/Control/Data In
(Digital). A 2.048 Mbit/s serial control &
10
13
Control/Data ST-BUS Out/Control/Data Out
(Digital). A 2.048 Mbit/s serial control &
11
12
14
15
13
16
14
17
15
19
16
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
21
20
19
18
17
16
15
22 PIN PDIP/CERDIP
LOUT
VBias
VRef
MS2
MS1
MS0
RegC
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
28 PIN PLCC
2
4
3
2
1
2
2
5
6
7
8
9
10
11
25
24
23
22
21
20
19
1
1
1
1
1
1
1
L
V
V
N
V
L
T
NC
LOUT DIS
Precan
OSC1
OSC2
NC
C4/TCK
MS2
NC
MS1
MS0
RegC
F0/CLD
NC
C
C
V
D
N
F
D