參數(shù)資料
型號(hào): MT8971BP
廠商: Mitel Networks Corporation
英文描述: ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit
中文描述: ISO2 -意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字用戶接口電路的數(shù)字網(wǎng)絡(luò)接口電路
文件頁數(shù): 16/20頁
文件大?。?/td> 390K
代理商: MT8971BP
MT8971B/72B
9-122
Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Duty cycle is measured at V
DD
/2 volts.
AC Electrical Characteristics
- Clock Timing - DN Mode (Figures 16 & 17)
.
Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes:
1)
When operating as a SLAVE the C4 clock has a 40% duty cycle.
2)
When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,
F
C
=2.5xf
C4
). The relative phase between these two clocks (
Φ
in Fig. 17) is not critical and may vary from
0 ns to t
C4P
. However, the relative jitter must be less than J
C
(see Figure 17).
Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ*
Max
Units
Test Conditions
1
I
N
P
U
T
S
Input Voltage
(L
IN)
(L
IN
)
(L
IN
)
V
IN
I
IN
Z
IN
f
C
T
C
DC
C
DC
C
5.0
V
pp
2
Input Current
-10
+10
μ
A
f
Baud
=160 kHz
f
Baud
=160 kHz
3
Input Impedance
20
40
k
4
Crystal/Clock Frequency
10.24
MHz
5
Crystal/Clock Tolerance
-100
0
+100
ppm
6a
Crystal/Clock Duty Cycle
40
50
60
%
Normal temp. & V
DD
Recommended at max./
min. temp. & V
DD
From OSC1 & OSC2 to V
SS
.
6b
Crystal/Clock Duty Cycle
45
50
55
%
7
Crystal/Clock Loading
C
L
C
o
R
Lout
33
50
pF
8
O
U
T
P
U
T
S
Output Capacitance
(L
OUT
)
(L
OUT
)
8
pF
9
Load Resistance
(V
Bias
, V
Ref
)
500
100
k
10
Load Capacitance
(L
OUT
)
(V
Bias
, V
Ref
)
C
Lout
0.1
20
pF
μF
Capacitance to V
Bias
.
11
Output Voltage
(L
OUT
)
V
o
3.2
4.3
4.6
V
pp
R
Lout
= 500
, C
Lout
= 20pF
Characteristics
Sym
Min
Typ*
Max
Units
Test Conditions
1
C4 Clock Period
t
C4P
t
C4W
t
F0S
t
F0H
t
F0W
J
C
244
ns
2
C4 Clock Width High or Low
90
122
150
ns
In Master Mode - Note 1
3
Frame Pulse Setup Time
50
ns
4
Frame Pulse Hold Time
50
ns
5
Frame Pulse Width
172
244
ns
6
10.24 MHz Clock Jitter (wrt C4)
-15
+15
ns
Note 2
Channel 31
Bit 0
Channel 0
Bit 7
Channel 0
Bit 6
F0b
C4
ST-BUS
BIT CELLS
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