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參數(shù)資料
| 型號： | MT8967AS |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | ISO2-CMOS Integrated PCM Filter Codec |
| 中文描述： | ISO2 - CMOS集成電路的PCM編解碼器 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 607K |
| 代理商： | MT8967AS |
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MT8960/61/62/63/64/65/66/67
Data Sheet
16
Zarlink Semiconductor Inc.
(See Figures 9a, 9b, 9c)
* Typical figures are at 25
°
C with nominal
±
5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 3:
The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to
C2i. The A/D and D/A functions are unaffected by changes in clock frequency.
Note 4:
This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i
will give an
undetermined state to the internally synchronized enable signal.
AC Electrical Characteristics
- Voltages are with respect to GNDD unless otherwise stated.
T
A
=0 to 70
°
C, V
DD
=5V
±
5%, V
EE
=-5V
±
5%, V
Ref
=2.5V
0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless
otherwise specified.
Characteristics
Sym.
Min.
Typ.*
Max
Units
Test Conditions
1
D
I
G
I
T
A
L
Clock Frequency
C2i
f
C
2.046
2.048
2.05
MHz
See Note 3
2
Clock Rise Time
C2i
t
CR
50
ns
3
Clock Fall Time
C2i
t
CF
50
ns
4
Clock Duty Cycle
C2i
40
50
60
%
5
Chip Enable Rise Time
F1i
t
ER
100
ns
6
Chip Enable Fall Time
F1i
t
EF
100
ns
7
Chip Enable Setup Time F1i
t
ES
50
ns
See Note 4
8
Chip Enable Hold Time
F1i
t
EH
25
ns
See Note 4
9
Output Rise Time
DSTo
t
OR
100
ns
10
Output Fall Time
DSTo
t
OF
100
ns
11
Propagation Delay Clock DSTo
to Output Enable
t
PZL
t
PZH
122
122
ns
ns
R
L
=10 K
to V
CC
12
Propagation Delay
Clock to Output
DSTo
t
PLH
t
PHL
100
100
ns
ns
C
L
=100 pF
13
Input Rise Time
CSTi
DSTi
t
IR
100
100
ns
ns
14
Input Fall Time
CSTi
DSTi
t
IF
100
100
ns
ns
15
Input Setup Time
CSTi
DSTi
t
ISH
t
ISL
25
0
ns
ns
16
Input Hold Time
CSTi
DSTi
t
IH
60
60
ns
ns
17
D
I
G
I
T
A
L
Propagation Delay
Clock to SD Output
SD
t
PCS
400
ns
C
L
= 100 pF
18
SD Output Fall Time
SD
t
SF
200
ns
C
L
= 20 pF
19
SD Output Rise Time
SD
t
SR
400
ns
20
Digital Loopback
Time DSTi to DSTo
t
DL
122
ns
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