參數(shù)資料
型號(hào): MT8962
廠商: Mitel Networks Corporation
元件分類: Codec
英文描述: Integrated PCM Filter Codec(集成PCM濾波器/編解碼器(用于數(shù)字遠(yuǎn)程通信))
中文描述: 集成濾波器的PCM編解碼器(集成的PCM濾波器/編解碼器(用于數(shù)字遠(yuǎn)程通信))
文件頁(yè)數(shù): 12/24頁(yè)
文件大?。?/td> 120K
代理商: MT8962
MT8960/61/62/63/64/65/66/67
ISO
2
-CMOS
6-30
Note 2:
AC Electrical Characteristics
- Voltages are with respect to GNDD unless otherwise stated.
T
A
=0 to 70
°
C, V
DD
=5V
±
5%, V
EE
=-5V
±
5%, V
Ref
=2.5V
±
0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless
otherwise specified.
V
OSIN
specifies the DC component of the digitally encoded PCM word.
* Typical figures are at 25
°
C with nominal
±
5V supplies. For design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics (cont’d)
Characteristics
Sym
Min
Typ*
Max
Units
Test Conditions
6
D
I
G
I
T
A
L
Output Low
DSTo
V
OL
V
OL
V
OH
V
OH
R
OUT
C
OUT
I
IN
R
IN
C
IN
V
OSIN
R
OUT
V
OSOUT
0.4
V
I
OUT
=1.6 mA
I
OUT
=1 mA
I
OUT
=-100
μ
A
I
OUT
=-1mA
V
OUT
=+1V
Output High Impedance
Voltage
SD
0-2
1.0
V
7
Output High
DSTo
4.0
V
Voltage
SD
0-2
4.0
V
8
Output Resistance
SD
3-5
1.0
2.0
K
9
Output Capacitance
DSTo
4.0
pF
10
A
N
A
L
O
G
Input Current
V
X
V
X
V
X
V
X
V
R
10.0
μ
A
M
V
EE
V
IN
V
CC
11
Input Resistance
10.0
12
Input Capacitance
30.0
pF
f
IN
= 0 - 4 kHz
See Note 2
13
Input Offset Voltage
+1.0
mV
14
Output Resistance
100
15
Output Offset Voltage V
R
100
mV
Digital Input= +0
Characteristics
Sym
Min
Typ*
Max
Units
Test Conditions
1
D
I
G
I
T
A
L
Clock Frequency
C2i
f
C
t
CR
t
CF
2.046
2.048
2.05
MHz
See Note 3
2
Clock Rise Time
C2i
50
ns
3
Clock Fall Time
C2i
50
ns
4
Clock Duty Cycle
C2i
40
50
60
%
5
Chip Enable Rise Time
F1i
t
ER
t
EF
t
ES
t
EH
t
OR
t
OF
t
PZL
t
PZH
t
PLH
t
PHL
t
IR
100
ns
6
Chip Enable Fall Time
F1i
100
ns
7
Chip Enable Setup Time F1i
50
ns
See Note 4
8
Chip Enable Hold Time
F1i
25
ns
See Note 4
9
Output Rise Time
DSTo
100
ns
10
Output Fall Time
DSTo
100
ns
11
Propagation Delay Clock DSTo
to Output Enable
122
122
ns
ns
R
L
=10K
to V
CC
C
L
=100 pF
12
Propagation Delay
Clock to Output
DSTo
100
100
ns
ns
13
Input Rise Time
CSTi
DSTi
100
100
ns
ns
14
Input Fall Time
CSTi
DSTi
t
IF
100
100
ns
ns
15
Input Setup Time
CSTi
DSTi
t
ISH
t
ISL
t
IH
25
0
ns
ns
16
Input Hold Time
CSTi
DSTi
60
60
ns
ns
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