參數(shù)資料
      型號(hào): MT8960
      廠商: Mitel Networks Corporation
      元件分類: Codec
      英文描述: ISO2-CMOS Integrated PCM Filter Codec
      中文描述: ISO2 - CMOS集成電路的PCM編解碼器
      文件頁(yè)數(shù): 20/32頁(yè)
      文件大?。?/td> 607K
      代理商: MT8960
      MT8960/61/62/63/64/65/66/67
      Data Sheet
      20
      Zarlink Semiconductor Inc.
      * Typical figures are at 25
      °
      C with nominal
      ±
      5V supplies. For design aid only: not guaranteed and not subject to production testing.
      Note 7:
      0dBm0=1.185 V
      RMS
      for
      μ
      -
      Law codec and 0dBm0=1.231 V
      RMS
      for A-Law codec.
      11
      A
      N
      A
      L
      O
      G
      Envelope Delay
      D
      AR
      210
      μ
      s
      @ 1004 Hz
      12
      Envelope Delay 1000-2600 Hz
      Variation with
      Frequency
      600-3000 Hz
      400-3200 Hz
      D
      DR
      90
      170
      265
      μ
      s
      μ
      s
      μ
      s
      Input Signal:
      400 - 3200 Hz digital
      sinewave at 0 dBm0
      13
      Gain Relative to
      Gain @ 1004 Hz
      (See Figure 11)
      <
      200 Hz
      200 Hz
      300-3000 Hz
      3300 Hz
      3400 Hz
      4000 Hz
      4600 Hz
      G
      RR
      -0.5
      -0.125
      -0.350
      -0.80
      0.125
      0.125
      0.125
      0.030
      -0.100
      -14.0
      -28.0
      dB
      dB
      dB
      dB
      dB
      dB
      dB
      0 dBm0 Input Signal
      Receive
      Filter
      Response
      14
      Crosstalk A/D to D/A
      CT
      TR
      -70
      dB
      0 dBm0 @ 1.02 kHz
      in A/D
      15
      Power Supply
      Rejection
      V
      DD
      V
      EE
      PSRR
      3
      PSRR
      4
      33
      35
      dB
      dB
      Input 50 mV
      RMS
      at
      1.02 kHz
      16
      Overload Distortion
      (See Fig. 15)
      Input frequency=1.02
      kHz
      AC Electrical Characteristics - Receive (D/A) Path
      - Voltages are with respect to GNDD unless otherwise stated.
      T
      A
      =0 to 70
      °
      C, V
      DD
      =5V
      ±
      5%, V
      EE
      =-5V
      ±
      5%, V
      Ref
      =2.5V
      ±
      0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
      Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
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      參數(shù)描述
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