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參數(shù)資料
| 型號： | MT8952BS |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| 中文描述： | 異意法半導體的CMOS總線⑩家庭HDLC協(xié)議控制器 |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 397K |
| 代理商： | MT8952BS |
MT8952B
ISO-CMOS
3-82
Timing is over recommended temperature & power supply voltages (V
=5V
±
5%, V
=0V, T
=–40 to 85
°
C).
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 25 - Serial Port Input and Output in ST-BUS Format (Internal Timing Mode)
1. Channels 0 to 4 can only be active on CDSTi and CDSTo in the Internal Timing Mode.
2. Clock input CKi can be either of the ST-BUS clocks C2i (2.048MHz) or C4i (4.096 MHz) in the Internal Timing Mode.
3. The Frame Pulse set up and hold time measurements are to be referenced from the falling edge of C4i or the rising edge of C2i depending on
the clock selected.
Note
:
Figure 26 - Test Load Circuits
Note
: Active Low to High impedance times are measured from the disabling signal edge to the time when V
out
has increased by 0.5 volts. Active High to
High impedance times are measured from the disabling signal edge to the time when V
out
has decreased by 0.5 volts.
AC Electrical Characteristics
- Serial Port in Internal Timing Mode - (Figure 25)
Voltages are with respect to ground (V
SS
) unless otherwise stated .
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Frame Pulse (F0i) width
t
F0iW
t
F0iS
t
F0iH
t
SToZL
t
SToZH
t
STiS
t
STiH
50
ns
2
Frame Pulse (F0i) setup time
30
ns
See note 3.
3
Frame Pulse (F0i) hold time
20
ns
See note 3.
4
CDSTo delay from clock input
125
ns
Test load circuit 1 (Fig. 26)
5
CDSTi setup time
20
ns
6
CDSTi hold time
65
ns
7
C2i clock period
tC2i
400
ns
8
C4i clock period
tC4i
200
ns
F0i
CKi
(C4i)
CKi
(C2i)
CDSTo
CDSTi
t
F0iW
t
F0iH
t
C4i
t
F0iS
t
C2i
t
SToZL
t
SToZH
HIGH IMPEDANCE
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
t
STiH
t
STiS
Ch. 31
Bit 0
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
From
output
under test
Test
point
C
L
Test load circuit- 1
V
DD
R
L
=1k
Test
point
From
output
under test
Test load circuit- 2
Test load circuit - 3
From
output
under test
C
L
C
L
Test
point
S
1
V
DD
V
SS
R
L
=1k
Note: S
is in position A
when measuring t
PLZ
and in position B when
measuring t
PHZ
. See
note below.
C
L
= 200 pF for
measurements
on Data Bus
150 pF for
measurements
on CDSTo
50 pF for
others
A
B
相關PDF資料 |
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|---|---|
| MT8952 | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952B | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952B-1 | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
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相關代理商/技術參數(shù) |
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|---|---|
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| MT8961 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS Integrated PCM Filter Codec |
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