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參數(shù)資料
| 型號(hào)： | MT8952B-1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| 中文描述： | 異意法半導(dǎo)體的CMOS總線⑩家庭HDLC協(xié)議控制器 |
| 文件頁(yè)數(shù)： | 7/22頁(yè) |
| 文件大小： | 397K |
| 代理商： | MT8952B-1 |
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ISO-CMOS
MT8952B
3-67
Order of Bit Transmission/Reception
The Least Significant Bit (LSB) corresponding to D0
on the data bus is transmitted first on the serial
output (CDSTo). On the receiving side, the first bit
received on the serial input (CDSTi) is considered as
the LSB and placed on D0 of the data bus.
Registers
There are several registers in the HDLC Protocol
Controller accessible to the associated micro-
processor via the data bus. The addresses of these
registers are given in Table 1 and their functional
details are given below.
FIFO Status Register (Read):
This register (Figure 4) indicates the status of
transmit and receive FIFOs and the received byte as
described below.
Figure 4 - FIFO Status Register
Rx Byte Status:
These two bits (D7 and D6) indicate
the status of the received byte ready to be read from
the receive FIFO. The status is encoded as shown in
Table 3.
Table 3. Received Byte Status
Rx FIFO Status:
These bits (D5 and D4) indicate the
status of receive FIFO as given by Table 4. The Rx
FIFO status bits are not updated immediately after
an access of the Rx FIFO (a read from the
microprocessor port, or a write from the serial port),
to avoid the existence of unrecoverable error
conditions.
When in external timing mode, the MT8952B must
receive two falling edges of the clock signal at the
CKi input before the Rx FIFO status bits will be
updated. When in internal 2.048 MHz timing mode,
the MT8952B must receive two falling edges of the
C2i clock before the Rx FIFO status bits will be
Table 4. Receive FIFO Status
updated. When in internal 4.096 MHz timing mode,
the MT8952B must receive four falling edges of the
C4i clock before the Rx FIFO status bit will be
updated (see the section on Receive Operation -
Normal Packets).
Tx FIFO Status:
These two bits (D3 and D2) indicate
the status of transmit FIFO as shown in Table 5.
Table 5. Transmit FIFO Status
The Tx FIFO status bits are updated in the same
manner as the Rx FIFO bits, except that in external
timing mode, and in internal 2.048 Mbps timing
mode, the Tx FIFO status bits are updated after two
falling edges of the CKi or the C2i signal (see the
section on Transmit Operation - Normal Packets).
Receive Data Register (Read):
Reading the Receive Data Register (Figure 5) puts
the first byte from the receive FIFO on the data bus.
The first bit of the data received on the serial input
(CDSTi) is considered to be the LSB and is available
on D0 of the data bus.
Figure 5 - Receive Data Register
Transmit Data Register (Write):
Writing to Transmit Data Register (Figure 6) puts the
data present on the data bus into the transmit FIFO.
The LSB (D0) is transmitted first.
D7
D6
D5
D4
D3
D2
D1
D0
Rx Byte
Status
Rx FIFO
Status
Tx FIFO
Status
LOW
LOW
Rx Byte
Status Bits
D7
0
0
1
1
Status
D6
0
1
0
1
Packet Byte
First Byte
Last Byte (Good FCS)
Last Byte (Bad FCS)
Rx FIFO
Status Bits
D5
0
0
1
1
Status
D4
0
1
0
1
Rx FIFO Empty
Less than or equal to 14 bytes
Rx FIFO Full
Greater than or equal to 15 bytes
Tx FIFO
Status Bits
D3
0
0
1
1
Status
D2
0
1
0
1
Tx FIFO Full
Greater than or equal to 5 bytes
Tx FIFO Empty
Less than or equal to 4 bytes
D7
D6
D5
D4
D3
D2
D1
D0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8952BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952BE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952BE1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLASTIC - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLASTIC - Rail/Tube |
| MT8952BP | 制造商:Microsemi Corporation 功能描述: 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8952BP1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:HDLC CONTROLLER, PLCC PB-FREE |
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