參數(shù)資料
型號(hào)： MT8941B
廠商： Mitel Networks Corporation
英文描述： CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL
中文描述： 意法半導(dǎo)體的CMOS總線(xiàn)⑩家庭高級(jí)T1/CEPT數(shù)字集群鎖相環(huán)
文件頁(yè)數(shù)： 7/22頁(yè)
文件大?。?/td> 131K
代理商： MT8941B
CMOS
MT8941B
7
When MS3 is HIGH, DPLL #2 operates in any of the
major modes selected by MS0 and MS1. When MS3
is LOW, it overrides the major mode selected and
DPLL#2 accepts an external clock of 4.096 MHz on
C4b (pin 13) to provide the 2.048 MHz clocks (C2o
and
C2o) and the 8 kHz frame pulse (F0b)
compatible with the ST-BUS format. The mode select
bit MS2 controls the direction of the signal on F0b
(pin 6).
When MS2 is LOW, the F0b pin is an 8 kHz frame
pulse input. This input is effective only when MS3 is
also LOW and pin C4b is fed by a 4.096 MHz clock,
which has a proper phase relationship with the
signal on F0b (refer Figure 18). Otherwise, the input
on pin F0b will have no bearing on the operation of
DPLL #2, unless it is in FREE-RUN mode as
selected by MS0 and MS1. In FREE-RUN mode,
the input on F0b is treated the same way as the
C8Kb input is in NORMAL mode. The frequency of
the signal on F0b should be 16 kHz for DPLL #2 to
lock and generate the ST-BUS compatible clocks at
4.096 MHz and 2.048 MHz.
When MS2 is HIGH, the F0b pin provides the frame
pulse output compatible with the ST-BUS format and
locked to the internal or external input signal as
determined by the other mode select pins.
Table 4 summarizes the modes of the two DPLL. It
should be noted that each of the major modes
selected for DPLL #2 can have any of the minor
modes, although some of the combinations are
Table 5. Functions of the Bidirectional Signals
in Each Mode
Notes:
i
: Input
o
: Output
X
: “don’t care” input. Connect to V
DD
or V
SS.
functionally similar. The required operation of both
DPLL #1 and DPLL #2 must be considered when
determining MS0-MS3.
The direction and frequency of each of the
bidirectional signals are listed in Table 5 for each of
the given modes in Table 4.
Jitter Performance and Lock-in Range
The output jitter of a DPLL is composed of the
intrinsic jitter, measured when no jitter is present at
the input, and the output jitter resulting from jitter on
the input signal. The spectrum of the intrinsic jitter
for both DPLLs of the MT8941B is shown in Figure 5.
The typical peak-to-peak value for this jitter is
0.07UI. The transfer function, which is the ratio of
the output jitter to the input jitter (both measured at a
particular frequency), is shown in Figure 6 for DPLL
#1 and Figure 7 for DPLL #2. The transfer function is
measured when the peak-to-peak amplitude of the
sinusoidal input jitter conforms to the following:
10 Hz - 100 Hz : 13.6
μ
s
100 Hz - 10 kHz : 20 dB/decade roll-off
> 10 kHz : 97.2 ns
The ability of a DPLL to phase-lock the input signal
to the reference signal and to remain locked depends
upon its lock-in range. The lock-in range of the DPLL
is specified in terms of the maximum frequency
variation in the 8 kHz reference signal. It is also
directly
affected
by
the
tolerance. Table 6 lists different values for the lock-in
range and the corresponding oscillator frequency
tolerance for DPLL #1 and DPLL #2. The smaller
the tolerance value, the larger the lock-in range.
oscillator
frequency
The T1 and CEPT standards specify that, for free
running equipment, the output clock tolerance must
be less than or equal to
±
32ppm and
±
50ppm
respectively. This requirement restricts the
Table 6. Lock-in Range vs. Oscillator Frequency
Tolerance
* Please refer to the section on “Jitter Performance and Lock-in
Range” for recommended oscillator tolerances for DPLL #1 & #2.
Mode
#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
F0b
(kHz)
i:8
i:X
o:8
o:8
i:8
i:X
o:8
o:8
i:8
i:16
o:8
o:8
i:8
i:X
o:8
o:8
C4b
(MHz)
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
C8Kb
(kHz)
i:X
i:8
i:X
i:8
i:X
o:8
i:X
o:8
i:X
i:X
i:X
i:X
i:X
o:8
i:X
o:8
CVb
(MHz)
o:1.544
o:1.544
o:1.544
o:1.544
i:1.544
i:1.544
i:1.544
i:1.544
o:1.544
o:1.544
o:1.544
o:1.544
i:2.408
i:2.408
i:2.408
i:2.408
Oscillator Clock*
Tolerance (
±
ppm)
5
10
20
32
50
100
150
175
Lock-in Range (
±
Hz)
DPLL #1
2.55
2.51
2.43
2.33
2.19
1.79
1.39
1.19
DPLL #2
1.91
1.87
1.79
1.69
1.55
1.15
.75
.55
相關(guān)PDF資料
PDF描述
MT8941BE CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL
MT8941BP CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL
MT8950 ISO-CMOS ST-BUS⑩ FAMILY Data Codec
MT8950AC ISO-CMOS ST-BUS⑩ FAMILY Data Codec
MT8952BC ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8941BE 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL
MT8941BP 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL
MT8941BP1 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209
MT8941BPR 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
MT8941BPR1 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG.TRUNK PLL EOL160209
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*