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參數(shù)資料
| 型號： | MT8941 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Advanced T1/CEPT Digital Trunk PLL |
| 中文描述： | 高級T1/CEPT數(shù)字集群鎖相環(huán) |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MT8941 |
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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Provides T1 clock at 1.544 MHz locked to an 8
kHz reference clock (frame pulse)
Provides CEPT clock at 2.048 MHz and ST-BUS
clock and timing signals locked to an internal or
external 8 kHz reference clock
Typical inherent output jitter (unfiltered)= 0.07 UI
peak-to-peak
Typical
jitter attenuation at: 10 Hz=23 dB,100
Hz=43 dB, 5 to 40 kHz
≥
64 dB
Jitter-free “FREE-RUN” mode
Uncommitted two-input NAND gate
Low power CMOS technology
Applications
Synchronization and timing control for T1
and CEPT digital trunk transmission links
ST- BUS clock and frame pulse source
Description
The MT8941B is a dual digital phase-locked loop
providing the timing and synchronization signals for the
T1 or CEPT transmission links and the ST-BUS. The
first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.
The MT8941B offers improved jitter performance over
the MT8940.
The two devices also have some
functional differences, which are listed in the section on
“Differences between MT8941B and MT8940”.
February 2005
Ordering Information
MT8941BE
24 Pin PDIP
MT8941BP
28 Pin PLCC
MT8941BPR
28 Pin PLCC
MT8941BP1
28 Pin PLCC*
MT8941BPR1 28 Pin PLCC*
*Pb Free Matte Tin
-40
°
C to +85
°
C
Tubes
Tubes
Tape & Reel
Tubes
Tape & Reel
MT8941B
Advanced T1/CEPT Digital Trunk PLL
Data Sheet
Figure 1 - Functional Block Diagram
F0i
C12i
MS0
MS1
MS2
MS3
C8Kb
C16i
Ai
Bi
Yo
V
DD
V
SS
RST
CVb
CV
ENCV
F0b
C4b
C4o
ENC4o
C2o
C2o
ENC2o
2:1 MUX
Variable
Clock
Control
Mode
Selection
Logic
DPLL #2
Input
Selector
Clock
Generator
Frame Pulse
Control
4.096 MHz
Clock
Control
2.048 MHz
Clock
Control
DPLL #1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8941BE | Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP1 | Advanced T1/CEPT Digital Trunk PLL |
| MT8941BPR | Round Conductor Flat Cable, 3849/96 30 AWG, .033 (0.85) |
| MT8941BPR1 | Advanced T1/CEPT Digital Trunk PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8941AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
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