參數(shù)資料
型號(hào)： MT8930CE
廠商： Mitel Networks Corporation
英文描述： CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit
中文描述： 意法半導(dǎo)體的CMOS總線⑩家庭用戶網(wǎng)絡(luò)接口電路
文件頁數(shù)： 18/42頁
文件大?。?/td> 323K
代理商： MT8930CE
MT8930C
9-50
distinguished by the fact that it has no “Last Byte”
status on any of its bytes.
iv) Idle Channel
While receiving the idle channel, the idle bit in the
HDLC status register remains set.
v) Transparent Data Transfer
By setting the Trans bit in the HDLC Control Register
2 to select the transparent data transfer, the receive
section will disable the protocol functions like Flag/
Abort/Idle detection, zero deletion, CRC calculation
and address comparison. The received data is
shifted in from the active port and written to receive
FIFO in bytewide format.
It should be noted that none of the protocol related
status or interrupt bits are applicable in transparent
data transfer state. However, the FIFO related status
and interrupt bits are pertinent and carry the same
meaning as they do while performing the protocol
functions.
vi) Receive Overflow
Receive overflow occurs when the receive section
attempts to load a byte to an already full receive
FIFO. All attempts to write to the full FIFO will be
ignored until the receive FIFO is read. When
overflow occurs, the rest of the present packet is
ignored as the receiver will be disabled until the
reception of the next opening flag.
Table 3. Master Control Register (Read/Write Add. 00000
B
)
Note 1:
Note 2:
These bits have no designated memory space and will read as the last values written to the microprocessor port.
The transmission of M=1 is used for a second level of multiframing.
Table 4. Control Register 1 (Write Add. 10000
B
)
BIT
NAME
DESCRIPTION
B7
NA
A ‘1’ will allow access to Control Register 1 and Master Status Register.
A ‘0’ will prevent it.
B6-B3
NA
(1)
Keep at ’0’ for normal operation.
B2
IRQ/NDA
The state of this pin will select the mode of the IRQ/NDA pin.
A ’0’ will enable the IRQ pin for HDLC interrupts.
A ’1’ will enable the New Data Available signal which identifies the access time to the
synchronous registers. (If NDA is enabled, the HDLC interrupts are disabled.)
A ’0’ will enable the transmission of the M
(2)
or S bit as selected in the NT Mode C-channel
Register (refer to Table 13). The selection of M or S is determined by the HALF signal
(refer to functional timing).
A ’1’ will disable this feature forcing the M and S bits to binary zero.
B1
M/Sen
B0
P/SC
The Parallel/Serial Control bit selects the source of the control channel. If ’0’, then the C-
channel Register is access through the ST-BUS stream. If ’1’, then the C-channel
Register is accessed through the microprocessor port.
BIT
NAME
DESCRIPTION
B7
NA
Keep at ‘0’ for normal operation.
B6
RxDIS
When set to ‘1’, this bit disables the S-Bus signal receiver. It can be used, for example, to
force INFO4 to INFO2 transition in the NT state machine while receiving INFO3 from the
TE.
B5-B0
NA
Keep at ‘0’ for normal operation.
相關(guān)PDF資料
PDF描述
MT8930CP CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit
MT8931C Subscriber Network Interface Circuit(用戶網(wǎng)絡(luò)接口電路（提供點(diǎn)到點(diǎn)或點(diǎn)到多點(diǎn)數(shù)字傳送）)
MT8940 T1/CEPT Digital Trunk PLL(T1/CEPT數(shù)字中繼鎖相環(huán))
MT8940 ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL
MT8940-1 ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8930CP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit
MT8930CPR 制造商:Microsemi Corporation 功能描述:
MT8931B 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit
MT8931BC 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit
MT8931BE 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit
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