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參數(shù)資料
| 型號(hào)： | MT8910-1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| 中文描述： | 意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字用戶線接口電路 |
| 文件頁(yè)數(shù)： | 1/26頁(yè) |
| 文件大?。?/td> | 419K |
| 代理商： | MT8910-1 |
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9-3
Features
Compatible with ISDN U-Interface standard
Over 40dB (
@
40 kHz) of loop attenuation
Full duplex transmission over single twisted
pair
Advanced echo cancelling technology
High performance 2B1Q line code
Full activation/deactivation state machine
QSNR and line attenuation diagnostics
Frame and superframe synchronization
On-chip 15 second timer
Insertion loss measurement test signal & quiet
mode
Mitel ST-BUS compatible
Single 5V power supply
Applications
ISDN NT1 and NT2 DSL interface
Digital PABX line cards and telephone sets
Digital multiplexers and concentrators
Pair gain system
Description
The MT8910-1 Digital Subscriber Line Interface
Circuit (DSLIC)
is designed to provide ISDN basic
rate access (2B+D) at the U-interface. Full duplex
digital transmission at 160 kbit/s on a single twisted
pair is achieved using echo cancelling hybrid (ECH)
technology. This, in conjunction with the high
performance 2B1Q line code, allows the DSLIC to
meet the loop length requirements of the digital
subscriber loops at the U-interface over the entire
non-loaded telephone loop plant.
The MT8910-1 is compatible with the complete
range of Mitel Semiconductor ISDN components
through the use of the ST-BUS interface.
Figure 1 - Functional Block Diagram
DSTi
CDSTi
MRST
F0b
C4b
SFb
F0od
MS0
MS1
NT/LT
CDSTo
DSTo
VSS
AVSS
VDD
AVDD
OSC2
OSC1
TSTin
TSTout TSTen VRef
VBias
Lin+
Lin-
Lout-
Lout+
Transmit
Interface
Control
Register
TRANSMIT/
RECEIVE TIMING
& CONTROL
INTERFACE
Status
Register
Receive
Interface
Scrambler
& Encoder
Framing
&
Maintenance
Descrambler,
Decoder &
Diagnostics
Jitter
Compen-
sator
Linear
Echo
Canceller
Non-
Linear
Compen-
sator
Decision
Feedback
Equalizer
Quantizer
DAC and
Tx Filter
Timing
Adaptation
Circuit
+
-
Tone
Detector
2nd Order
PDM ADC
FIR
Digital Filter
Bias &
Voltage Ref.
Ordering Information
MT8910-1AC
28 Pin Ceramic DIP
MT8910-1AP
44 Pin PLCC
0
°
C to +70
°
C
ISSUE 1
August 1993
MT8910-1
Digital Subscriber Line Interface Circuit
Preliminary Information
CMOS ST-BUS
FAMILY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8910-1AC | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8910-1AP | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8920 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B-1 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8910-1AC | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8910-1AP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8920 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920AE | 制造商:Mitel Networks Corporation 功能描述: |
| MT8920B | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
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