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參數(shù)資料
| 型號： | MT88V32AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 8 x 4 High Performance Video Switch Array |
| 中文描述： | 8 × 4高性能視頻開關(guān)陣列 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 237K |
| 代理商： | MT88V32AP |
MT88V32
Preliminary Information
3-62
DC Electrical Characteristics are over recommended temperature range and recommended power supply voltages.
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Algebraic convention is adopted in this data sheet where the most negative value is a minimum and the most positive value is a
maximum.
Timing is over recommended temperature range.
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
Valid for V
EE
=-7V, V
DD
=+5V and V
DC
=-2.0V. Error will increase slightly if input is biased differently.
Input test signal: 700mV ramp biased @ -2.0Vdc with a superimposed video signal of 285Vrms @ 3.58 MHz.
Guaranteed by design and characterization and not subject to production testing.
DC Electrical Characteristics
- Digital Input/Output
Voltages are with respect to V
DD
=5V, V
EE
=-7V, V
SS
=0V, unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Input logic "1" level
V
IH
V
IH
V
IL
V
IL
I
LEAK
V
OH
I
OH
V
OL
I
OL
I
OZ
2
V
V
V
V
μ
A
V
mA
V
mA
μ
A
3.3
V
EE
=V
SS
=0, V
DD
=12V
2
Input logic "0" level
0.8
0.8
±10
V
DD
V
EE
=V
SS
=0, V
DD
=12V
V
IND
=V
DD
or V
SS
I
OH
=7mA@V
OH
=2.4V
source V
OH
=2.4V
I
OL
=2mA@V
OL
=0.4V
sink V
OL
=0.4V
V
O
=0 to V
DD
3
4
5
6
7
8
Input leakage (digital pins)
Data output high voltage
Data output high current
Data output low voltage
Data output low current
Data high impedance leakage
±1
2.4
7
V
SS
2
20
0.4
5
1
10
AC Electrical Characteristics
- Crosspoint Performance
- Voltages are with respect to V
DD
=+5V, V
DC
=0,
V
EE
=-7V, V
SS
=0V, unlesss otherwise stated. Also applicable for V
EE
=V
SS
=0, V
DD
=+12V, V
DC
=(V
DD
+V
EE
)/2.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
On-state Xi capacitance
On-state Yi capacitance
Off-state Xi capacitance
Off-state Yi capacitance
Break-before-Make interval
Single channel feedthrough
(all crosspoints open)
(see Fig. 8)
Single channel feedthrough
(all crosspoints closed)
(See Fig. 9)
C
Xi (on)
C
Yi (on)
C
Xi (off)
C
Yi (off)
t
open
FDT
56
56
30
15
pF
pF
pF
pF
ns
1 Xi to 1 Yi
1 Yi to 1 Xi
10
-80
-62
dB
dB
R
S
= R
L
=75
V
IN
=0.6Vpp @ 5MHz
V
IN
=0.6Vpp @ 15MHz
R
IN
= 10
,
R
L
= 10k
V
IN
=0.6Vpp @ 5MHz
V
IN
=0.6Vpp @ 15MHz
R
IN
= 75
,
R
L
= 10k
V
IN
=0.6Vpp @ 5MHz
V
IN
=0.6Vpp @ 15MHz
R
IN
= 10
,
R
L
= 10k
V
IN
=0.6Vpp @ 5MHz
7
X
talk
(sc)
-85
-68
dB
dB
X
talk
(sc)
-70
-50
-55
dB
dB
dB
8
All channel crosstalk
(all crosspoints closed)
(See Fig. 10)
Frequency Response
(see Fig.11)
Differential Phase Error
X
talk
(ac)
9
f
3dB
200
MHz
R
S
= R
L
=50
10
DP
0.05
o
See Note
, R
S
= 50
,
R
L
= 75
See Note
, R
S
= 50
,
R
L
= 75
11
Differential Gain Error
DG
0.11
%
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