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MT88E43B
Preliminary Information
56
In CIDCW service, information about an incoming
caller is sent to the subscriber, while he/she is
already engaged in another call. A CPE Alerting
Signal (CAS) indicates the arrival of CIDCW
information. The MT88E43B can detect the CAS and
then be setup to demodulate the incoming FSK
containing the CIDCW information.
Functional Description
Detection of CLIP/CID Call Arrival Indicators
The circuit in Figure 3 illustrates the relationship
between the TRIGin, TRIGRC and TRIGout signals.
Typically, the three pin combination is used to detect
an event indicated by an increase of the TRIGin
voltage from V
SS
to above the Schmitt trigger high
going
threshold
V
T+
characteristics).
(see
DC
electrical
Figure 3 shows a circuit to detect any one of three
CLIP/CID call arrival indicators: line reversal, ring
burst and ringing.
Line Reversal Detection
Line reversal, or polarity reversal on the A and B
wires indicates the arrival of an incoming CDS call,
as specified in SIN227. When the event (line
reversal) occurs, TRIGin rises past the high going
Schmitt threshold V
T+
and
normally high, is pulled low. When the event is over,
TRIGin falls back to below the low going Schmitt
threshold V
T-
and
TRIGout returns high. The
TRIGout, which is
components R5 and C3 (see Figure 3) at TRIGRC
ensure a minimum TRIGout low interval.
In a TE designed for CLIP, the TRIGout high to low
transition may be used to interrupt or wake-up the
microcontroller. The controller can thus be put into
power-down mode to conserve power in a battery
operated TE.
Ring Burst Detection
CCA does not support the dual tone alert signal
(refer to Dual Tone Alert Signal Detection section).
Instead, CCA requires that the TE be able to detect a
single burst of ringing (duration 200-450ms) that
precedes CLIP FSK data. The ring burst may vary
from 30 to 75Vrms and is approximately 25Hz.
Again in a TE designed for CCA CLIP, the TRIGout
high to low transition may be used to interrupt or
wake-up the microcontroller. The controller can thus
be put into power-down mode to conserve power in a
battery operated TE.
Ring Detection
In Bellcore’s CND/CNAM scheme, the CID FSK data
is transmitted between the first and second ringing
cycles. The circuit in Figure 3 will generate a ring
envelope signal (active low) at TRIGout for a ring
voltage of at least 40Vrms. R5 and C3 filter the ring
signal to provide an envelope output.
The diode bridge shown in Figure 3 works for both
single ended and balanced ringing. A fraction of the
Figure 3 - Circuit to Detect Line Reversal, Ring Burst and Ringing
Tip/A
C1=100nF
R1=499K
Ring/B
C2=100nF
R2=499K
MT88E43B
TRIGout
To Microcontroller
R3=200K
R
R
C
TRIGRC
TRIGin
V
DD
V1
V2
V3
V4
max V
T+
= 0.68 V
DD
min V
T+
= 0.48 V
DD
The application circuit must ensure that,
V
TRIGin
>max V
T+
where max V
T+
=3.74V @V
DD
=5.5V.
Tolerance to noise between A/B and V
SS
is:
max V
noise
= (min V
T+
)/0.30+0.7 = 5.6Vrms @4.5V V
DD
where min V
T+
= 2.16V @V
DD
=4.5V.
Suggested R
5
C
3
component values:
R5 from 10K
to 500K
C3 from 47nF to 0.68
μ
F
An example is C3=220nF, R5=150K
; TRIGout low from
21.6ms to 37.6ms after the TRIGin signal stops
triggering the circuit.
Notes:
To determine values for C3 and R5:
R5C3 = -t / ln(1-V
TRIGRC
/V
DD
)