參數(shù)資料
型號(hào): MT88E39
廠商: Mitel Networks Corporation
英文描述: CMOS Calling Number Identification Circuit(CNIC1.1)
中文描述: 主叫號(hào)碼識(shí)別的CMOS電路(CNIC1.1)
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 98K
代理商: MT88E39
MT88E39
Advance Information
5-10
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. The device will stop functioning within this time, but more time may be required to reach I
DDQ
.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. FSK input data at 1200
±
12 baud.
2. OSC1 at 3.579545 MHz
±
0.2%.
3. 10k to V
SS
, 50pF to V
SS.
4. 10k to V
, 50pF to V
.
5. Function of signal condition.
6. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only, not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Timing
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
PWDN
OSC1
Power-up time
t
PU
t
PD
t
IAL
t
IAH
50
ms
2
Power-down time
100
1000
μ
s
1
3
CD
Input FSK to CD low delay
25
ms
4
Input FSK to CD high delay
10
ms
5
Hysteresis
10
ms
AC Electrical Characteristics
- 3-Wire FSK Interface Timing (Mode 0)
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
DATA
Rate
1188
1200
1212
bps
1, 6
2
Input FSK to DATA delay
t
IDD
t
R
t
F
t
DCD
t
CDD
1
5
ms
3
DATA
DCLK
Rise time
200
ns
3
4
Fall time
200
ns
3
5
DATA to DCLK delay
6
416
μ
s
μ
s
1, 2, 5, 6
6
DCLK to DATA delay
6
416
1, 2, 5, 6
7
DCLK
Frequency
1200.4
1202.8
1205.2
Hz
2
8
High time
t
CH
t
CL
t
CRD
415
416
417
μ
s
μ
s
μ
s
2
9
Low time
415
416
417
2
10
DCLK
DR
DCLK to DR delay
415
416
417
2
11
DR
Rise time
t
RR
t
FF
t
RL
10
μ
s
4
12
Fall time
200
ns
4
13
Low time
415
416
417
μ
s
2
AC Electrical Characteristics
- 3-Wire FSK Interface Timing (Mode 1)
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
DCLK
Frequency
f
DCLK1
1
MHz
See Fig. 12
2
Duty Cycle
30
70
%
3
Rise Time
100
ns
4
DCLK
DR
DCLK low setup time to DR
t
DDS
t
DDH
500
ns
See Fig. 12
5
DCLK low hold time to DR
500
ns
See Fig. 12
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