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參數資料
| 型號： | MT8870DC-1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ISO2-CMOS Integrated DTMF Receiver |
| 中文描述： | ISO2 - CMOS集成雙音多頻接收器 |
| 文件頁數： | 2/12頁 |
| 文件大?。?/td> | 215K |
| 代理商： | MT8870DC-1 |
MT8870D/MT8870D-1
ISO
2
-CMOS
4-12
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
18
20
1
1
IN+
Non-Inverting Op-Amp
(Input)
.
2
2
IN-
Inverting Op-Amp
(Input)
.
3
3
GS
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
4
V
Ref
Reference Voltage (Output).
Nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig. 6
and Fig. 10).
5
5
INH
Inhibit (Input).
Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
6
6
PWDN
Power Down (Input).
Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7
8
OSC1
Clock
(Input)
.
8
9
OSC2
Clock
(Output)
. A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
9
10
V
SS
TOE
Ground
(Input)
. 0V typical.
10
11
Three State Output Enable (Input).
Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
11-
14
12-
15
Q1-Q4
Three State Data (Output).
When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15
17
StD
Delayed Steering (Output).
Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
TSt
.
Early Steering (Output).
Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
16
18
ESt
17
19
St/GT
Steering Input/Guard time (Output) Bidirectional.
A voltage greater than V
TSt
detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
TSt
frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18
20
V
DD
NC
Positive power supply (Input)
. +5V typical.
7,
16
No Connection.
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
18 PIN CERDIP/PLASTIC DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
20 PIN SSOP/TSSOP
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
相關PDF資料 |
PDF描述 |
|---|---|
| MT8870DE-1 | ISO2-CMOS Integrated DTMF Receiver |
| MT8870DN-1 | ISO2-CMOS Integrated DTMF Receiver |
| MT8870D | Integrated DTMF Receiver(完全雙音多頻信號（DTMF）接收器（集成了濾波器和數字譯碼器功能）) |
| MT8870D-1 | Integrated DTMF Receiver(完全雙音多頻信號（DTMF）接收器（集成了濾波器和數字譯碼器功能）) |
| MT8870 | () |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MT8870DE | 制造商:Microsemi Corporation 功能描述: |
| MT8870DE1 | 制造商:Microsemi Corporation 功能描述:DTMF RX 3.58MHZ CMOS 5V 18PDIP - Rail/Tube 制造商:Microsemi Corporation 功能描述:Pb Free DTMF RECEIVER DIP 制造商:Zarlink Semiconductor Inc 功能描述:DTMF RX 3.58MHZ CMOS 5V 18PDIP - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:Pb Free DTMF RECEIVER DIP |
| MT8870DE-1 | 制造商:Microsemi Corporation 功能描述:DTMF RX 3.58MHZ CMOS 5V 18PDIP - Rail/Tube 制造商: 功能描述: 制造商:undefined 功能描述: |
| MT8870DE1-1 | 制造商:Microsemi Corporation 功能描述:DTMF RX 3.58MHZ CMOS 5V 18PDIP - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:DTMF RX 3.58MHZ CMOS 5V 18PDIP - Rail/Tube |
| MT8870DN | 制造商:Microsemi Corporation 功能描述: |
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