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參數(shù)資料
| 型號： | MT80C51T-16R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1 MM HEIGHT, QFP-44 |
| 文件頁數(shù)： | 26/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MT80C51T-16R |
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217
2466T–AVR–07/10
ATmega16(L)
Example:
ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)
Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts
the result: ADCL = 0x70, ADCH = 0x02.
ADC Multiplexer
Selection Register –
ADMUX
Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 83. If these bits are
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
Table 82. Correlation between Input Voltage and Output Codes
V
ADCn
Read code
Corresponding Decimal Value
V
ADCm + VREF/GAIN
0x1FF
511
VADCm + 511/512 VREF/GAIN
0x1FF
511
V
ADCm + 510/512 VREF/GAIN
0x1FE
510
...
VADCm + 1/512 VREF/GAIN
0x001
1
V
ADCm
0x000
0
VADCm - 1/512 VREF/GAIN
0x3FF
-1
...
V
ADCm - 511/512 VREF/GAIN
0x201
-511
VADCm - VREF/GAIN
0x200
-512
Bit
765
4321
0
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
ADMUX
Read/Write
R/W
Initial Value
000
0000
0
Table 83. Voltage Reference Selections for ADC
REFS1
REFS0
Voltage Reference Selection
0
AREF, Internal Vref turned off
0
1
AVCC with external capacitor at AREF pin
10
Reserved
1
Internal 2.56V Voltage Reference with external capacitor at AREF pin
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